Design and modeling of a clock data recovery (CDR) circuit /
Clock data recovery (CDR) circuits are in high demand due to development in communication technology such as improvements in transmit/receive processing and GHz transfer bandwidths via wired and wireless media. Large bandwidth data with high transfer rates encounter several major problems at the rec...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
Kuala Lumpur:
Kulliyyah of Engineering, International Islamic University Malaysia,
2013
|
| Subjects: | |
| Online Access: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Clock data recovery (CDR) circuits are in high demand due to development in communication technology such as improvements in transmit/receive processing and GHz transfer bandwidths via wired and wireless media. Large bandwidth data with high transfer rates encounter several major problems at the reception. Electrical signals are easily distorted with large bandwidth data when transmitted at high speeds. Existence of noise will cause disturbance or undesired signals at the output of the system. Minimizing the effects of jitter in CDR system is important to protect the signal from disturbance and to maintain low phase noise. A 5 Gbps clock data recovery circuit using PLL approach is proposed in this work. Hardware Description language, Verilog-AMS has been implemented as a modeling language for CDR using SMASH Dolphin Integrated software. The architecture of the proposed PLL CDR circuits incorporates a phase detector, RLC low-pass filter, voltage-controlled oscillator, and divider. Evaluation of the CDR performance is based on the design, frequency, transfer rate, supply voltage, and phase noise. The proposed circuit has a simple configuration powered using low supply of 1.0 V and operates in high speed of 5 Gbps. The phase noise performance is measure using four different offsets. Less phase noise of -130.29 dBc/Hz is generated without jitter added on it. To simulate jitter from 1 MHz to 100 GHz a pulse is added in each block of the CDR circuit and the circuit's performance is evaluated. CDR with jitter from 10 GHz up to 100 GHz at VCO produces the highest phase noise at the output port of -125.10 dBc/Hz. The PLL-based CDR circuit is affected when jitter pulses is added at the VCO. The proposed PLL-based CDR circuit is suitable for PCIe application with 5 Gbps transfer rate, low supply voltage, and has low phase noise. |
|---|---|
| Physical Description: | xvii, 99 leaves : ill. ; 30cm. |
| Bibliography: | Includes bibliographical references (leaves 82-86). |