Design and analysis of multi valued analog to digital converter /
Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Kuala Lumpur :
Kulliyyah of Engineering, International Islamic University Malaysia,
2012
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| Subjects: | |
| Online Access: | http://studentrepo.iium.edu.my/handle/123456789/4440 |
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| Summary: | Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high wiring complexity is increased packing complexity with increased number of pins. Therefore, high density layout must be used for data bus both in the silicon and on the printed circuit board. Second implication is increased cross-talk noise which is one of the limiting factors in design of high-speed and sophisticated ICs, especially in a low-power voltage environment and high-speed chips for arithmetic applications. Alternate approaches for design of integrated circuits for arithmetic operations that would use standard complementary metal oxide semiconductor (CMOS) technology and address the above issues have been proposed. One possible solution of high wiring complexity, without affecting performance of a chip, is injecting more than two levels of signals into a wire. This is known as multiple-valued logic (MVL), however, due to narrow voltage margins, especially in low power designs, current is proposed as a better approach to MVL design. MVL has been studied extensively due to its potential advantages in chips performing arithmetic intensive operations. A higher radix (radix-4) MVL ADC has been proposed to reduce circuit complexity, size and power. The circuits operation and functionality is verified by using Orchad PSpice 16.0 based on CMOS BSIM V3 0.13μm process parameters. It is found that the circuit can generate up to 256 bit with code width 62.5nA and sampling rate of 500 kHz. The proposed circuit also consumed less power (197μW) compared to others. The circuit is less complexity and performance is compared to others. Hence, the proposed ADC design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on MVL design. |
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| Item Description: | Abstract in English and Arabic. "A dissertation submitted in fulfilment of the requirement for the degree of Master of Science in Computer and information Engineering." --On t. p. |
| Physical Description: | xv, 129 leaves : ill. ; 30cm. |
| Bibliography: | Includes bibliographical references (leaves 79-84). |