Investigation of 4T CMOS active pixel sensor readout circuit's electrical properties for radiation environment /
CMOS Active Pixel Sensor (APS) is widely used in pixel sensing array devices i.e. image sensor in digital camera. The application of CMOS APS had cover wide niche including space application like satellites and medical application such as X-ray scanner. Radiation environment such as the outer space...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Kuala Lumpur :
Kulliyyah of Engineering, International Islamic University Malaysia,
2018
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| Subjects: | |
| Online Access: | http://studentrepo.iium.edu.my/handle/123456789/4913 |
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| Summary: | CMOS Active Pixel Sensor (APS) is widely used in pixel sensing array devices i.e. image sensor in digital camera. The application of CMOS APS had cover wide niche including space application like satellites and medical application such as X-ray scanner. Radiation environment such as the outer space had made CMOS APS vulnerable to the space radiation and may introduce defects. The present of radiation degraded the performance of CMOS APS by generated a high transient currents also known as noise and leakage current, in some cases the radiation might induce a bit-flip error. That type of radiation is known as Single Event Transient (SET). The SET is commonly considered as a soft error as the damage is not permanent. However, as the technology decreasing in scale the semiconductor devices have become more vulnerable towards SET. Given that, to conduct an experimental approach on radiation environment are dangerous and expensive, TCAD simulation is a good alternative on better understanding the effect of SET on semiconductor device. Silvaco Atlas and Silvaco MixedMode are two powerful TCAD tools that able to demonstrate the physical device structure, the doping contour, simulating space radiation i.e. SEU and also the current responses toward the energetic particles in device structure level. The 4T CMOS APS readout circuit with technology variant from 180nm to 32nm were simulated with various Linear Energy Transfer (LET) magnitudes/ Single Event Upset (SEU) density ranging from 3.3 to 67.7 Mev.cm2/mg. A radiation hardness technique which is Silicon on Insulator (SOI) was proposed. The aims of this research are 1) to characterize the SET effects towards 4T CMOS APS readout circuit, 2) to investigate the effects of SET on technology scaling and introduce radiation hardness on the 4T CMOS APS readout circuit. LET magnitudes is the density of energy transfer from ionizing particles (e.g. ions, electrons, photon and etc.) strike. These SET effects are characterized into peak current amplitude, excess drain current, cumulative charge, and track cumulative charge collection. Several set of simulations were conducted in order to find the most sensitive nodes, technology and the electrical characteristic for each SEU densities before simulating with and without the radiation hardness. After simulated with 3.3 MeV.cm2/mg, the 180nm 4T CMOS APS readout circuit shown the highest leakage current with the magnitude of 0.347mA at 4e-11s. This stated an increment of 1725% from the reference signal. Two type of device structures with 180nm technology were simulated with 3.3 MeV.cm2/mg of LET magnitude, the bulk based 4T CMOS APS has the highest leakage current 9.456e¬-5 A while the SOI based 4T CMOS APS is the lowest by a huge margin which is around 4.784e-5 A. There is about 49.41% of percentage different between bulk based 4T CMOS APS with SOI based 4T CMOS APS in radiation tolerant. SOI based 4T CMOS APS can withstand 49.41% more radiation than bulk based. The SOI radiation technique helps in reducing the radiation damage. |
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| Physical Description: | xv, 103 leaves : colour illustrations ; 30cm. |
| Bibliography: | Includes bibliographical references (leaves 79-81). |