Effect of single event upset on 6T and 12T static random access memory for different CMOS technologies /
Static random access memory cells (SRAMs) are high-speed semiconductor memory that uses a flip-flop to store each bit. Almost four decades ago, the effect of radiation on this high-speed semiconductor device was discovered when the first satellite experienced serious issues caused by the high-energy...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
Kuala Lumpur :
Kulliyyah of Engineering, International Islamic University Malaysia,
2017
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| Subjects: | |
| Online Access: | Click here to view 1st 24 pages of the thesis. Members can view fulltext at the specified PCs in the library. |
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| Summary: | Static random access memory cells (SRAMs) are high-speed semiconductor memory that uses a flip-flop to store each bit. Almost four decades ago, the effect of radiation on this high-speed semiconductor device was discovered when the first satellite experienced serious issues caused by the high-energy particles present in Van Allen belts. Since then, space and military communities have made an extensive research to study these effects on SRAMs in a harsh radiation environment, driven by all the potential of this high-speed memory in space missions, satellite, and advanced weapon. The study of radiation effect is vital as high energetic particles has limited the reliability of semiconductor memory, especially SRAMs. High performances and high-density SRAMs are prone to radiation-induced single event upsets (SEU) which found in most satellite orbits. SEU can cause a significant change in a device such as data flipping from '1' to '0' or vice versa. To protect SRAMs from SEU, it is necessary to study the parameters considered in SEU measurements that are critical LET and critical charge. Silvaco Gateway software circuit simulation have been a great alternative to studying SEU compared to the traditional way (involving actual exposure to cosmic ray by high altitude environment or simulation of cosmic ray environment by accelerations) which are expensive, complicated and off limited access. This work presents a Silvaco simulation in determining the critical LET and critical charge for 6T and 12T SRAMs at different CMOS technologies (130nm, 90nm, 65nm, 45nm, 32nm and 22nm). In this work, the double exponential current pulse (which is represented as LET) was injected at the most sensitive region is in SRAMs which is the drain node when the NMOS transistor is OFF. From the results, it found that downscaling the CMOS technologies, 12T SRAM is less vulnerable to SEU compared to conventional 6T SRAMs. Besides, from the calculated Qcrit, it is also found that 12T SRAM can store more collected charge (Qc), hence decreasing the probability occurrences of SEU as bit flip will occur when the Qc exceed the Qcrit. |
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| Physical Description: | xvi, 85 leaves : illustrations ; 30cm. |
| Bibliography: | Includes bibliographical references (leaves 59-61). |