Fast-Lock Low -Jitter Delay Locked Loop

In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.

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Bibliographic Details
Main Author:	Soh, Lip Kai
Format:	Thesis
Published:	2007
Subjects:	TK7800-8360 Electronics
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id	my-mmu-ep.1224
record_format	uketd_dc
spelling	my-mmu-ep.12242010-08-19T05:56:49Z Fast-Lock Low -Jitter Delay Locked Loop 2007-12 Soh, Lip Kai TK7800-8360 Electronics In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed. 2007-12 Thesis http://shdl.mmu.edu.my/1224/ http://myto.perpun.net.my/metoalogin/logina.php masters Multimedia University Research Library
institution	Multimedia University
collection	MMU Institutional Repository
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Soh, Lip Kai Fast-Lock Low -Jitter Delay Locked Loop
description	In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.
format	Thesis
qualification_level	Master's degree
author	Soh, Lip Kai
author_facet	Soh, Lip Kai
author_sort	Soh, Lip Kai
title	Fast-Lock Low -Jitter Delay Locked Loop
title_short	Fast-Lock Low -Jitter Delay Locked Loop
title_full	Fast-Lock Low -Jitter Delay Locked Loop
title_fullStr	Fast-Lock Low -Jitter Delay Locked Loop
title_full_unstemmed	Fast-Lock Low -Jitter Delay Locked Loop
title_sort	fast-lock low -jitter delay locked loop
granting_institution	Multimedia University
granting_department	Research Library
publishDate	2007
_version_	1747829320744697856

Fast-Lock Low -Jitter Delay Locked Loop

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