Design Of An ATM Based Multicast Connection
Asynchronous Transfer Mode (ATM) networks have emerged as a promising technology in realization of future broadband integrated services digital networks (B-ISDN). Multipoint communication services are considered a basic functionality in ATM switches to meet the future multimedia applications. In fac...
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| Format: | Thesis |
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2002
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| Summary: | Asynchronous Transfer Mode (ATM) networks have emerged as a promising technology in realization of future broadband integrated services digital networks (B-ISDN). Multipoint communication services are considered a basic functionality in ATM switches to meet the future multimedia applications. In fact, multicasting functionality is an important criterion in judging the powerfulness and extendibility of ATM switches. In this dissertation, a new architecture has been proposed to implement the ATM multicast switch . The switch architecture consists of a stack of binary trees and a bundle of modified Batcher's sorting networks. The basic building blocks are small, and re used to construct the large-scale ATM switches. This modular architecture provides multicast services and priority sorting functions. The input and output switching modules are completely partitioned, and this partitioned switch fabric provides a flexible distributed architecture. To perform the multicast functionality in binary trees, a new addressing scheme called Binary Partition Addressing Scheme (BiPAS) has been proposed. Another important characteristic in the design is the employment of a buffering scheme called hybrid shared memory and dedicated output buffering scheme which manage to reduce the memory requirement in the switch drastically. The performance of the proposed switch is evaluated in terms of switch throughput, average cell delay, and cell loss probability. The results in numerical analysis indicate a satisfactory approximation to our simulation results. The new architecture is evaluated in other aspects, which include overhead, complexity , and scalability issue. Subsequently, our results are compared with some architecture achieves a satisfactory throughput and offers the advantage of lesser cell loss in the switch. Such contribution is significant particularly for data services with low cell loss requirement and high latency-constraint. |
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