Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance

Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance

The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consumption and enhance the variability tolerance against process, voltage, temperature (PVT) and aging effect. The cell performs write operation using separate write signal WS instead of wordline WL to re...

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Main Author: Saadatzi, Mohammadsadegh
Format: Thesis
Published: 2015
Subjects:
TK7800-8360 Electronics
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spelling my-mmu-ep.68952017-09-07T10:49:44Z Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance 2015-12 Saadatzi, Mohammadsadegh TK7800-8360 Electronics The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consumption and enhance the variability tolerance against process, voltage, temperature (PVT) and aging effect. The cell performs write operation using separate write signal WS instead of wordline WL to reduce the discharging activity at the write bitline in order to save the dynamic power and enhance the write ability. Due to stack effect, the read leakage current is reduced during write operation. The lower voltage drops on respective bitline, lower leakage current and lower parasitic capacitance results 60.4% lower write power and 52.8% lower read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell is maintained even power supply is reduced to 300mV. As process variation becoming growing concern in deep sub-micron devices, it is necessary to study the operation of the ratioed structure under process variations and device mismatch. The global and local variations can cause the traditional ratioed logic to lose functionality. The proposed cell has been investigated under process, temperature and voltage (PVT) variations during read/write operations and hold mode which shows higher immunity towards the PVT variation. 2015-12 Thesis http://shdl.mmu.edu.my/6895/ http://library.mmu.edu.my/diglib/onlinedb/dig_lib.php masters Multimedia University Faculty of Engineering and Technology
institution Multimedia University
collection MMU Institutional Repository
topic TK7800-8360 Electronics
spellingShingle TK7800-8360 Electronics
Saadatzi, Mohammadsadegh
Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
description The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consumption and enhance the variability tolerance against process, voltage, temperature (PVT) and aging effect. The cell performs write operation using separate write signal WS instead of wordline WL to reduce the discharging activity at the write bitline in order to save the dynamic power and enhance the write ability. Due to stack effect, the read leakage current is reduced during write operation. The lower voltage drops on respective bitline, lower leakage current and lower parasitic capacitance results 60.4% lower write power and 52.8% lower read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell is maintained even power supply is reduced to 300mV. As process variation becoming growing concern in deep sub-micron devices, it is necessary to study the operation of the ratioed structure under process variations and device mismatch. The global and local variations can cause the traditional ratioed logic to lose functionality. The proposed cell has been investigated under process, temperature and voltage (PVT) variations during read/write operations and hold mode which shows higher immunity towards the PVT variation.
format Thesis
qualification_level Master's degree
author Saadatzi, Mohammadsadegh
author_facet Saadatzi, Mohammadsadegh
author_sort Saadatzi, Mohammadsadegh
title Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
title_short Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
title_full Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
title_fullStr Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
title_full_unstemmed Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance
title_sort design of power efficient 32-kilobit memory compiler for variability tolerance
granting_institution Multimedia University
granting_department Faculty of Engineering and Technology
publishDate 2015
_version_ 1747829643087446016

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