Cache coherence protocols in multi-processor / Fatin Najihah Razlan
The data coherence in the cache systems in multi-processors is expected to be more precise and reliable. There is no doubt that many approach has been taken in order to achieve that purpose. This thesis describes one of the approaches which is the cache coherence protocols in multiprocessor. A cache...
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| Format: | Thesis |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/102850/1/102850.pdf |
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| Summary: | The data coherence in the cache systems in multi-processors is expected to be more precise and reliable. There is no doubt that many approach has been taken in order to achieve that purpose. This thesis describes one of the approaches which is the cache coherence protocols in multiprocessor. A cache coherence protocol ensures the data consistency of the system. Typical modern microprocessors are currently built with multicore architecture that will involve data transfers between from one cache to another. By applying cache coherence protocols to each of the caches, the coherency problem can be solved. With this resolution, simulations of the applied cache coherence protocols can be each presented to walk-through the coherency processes in multi-processor. This simulation is developed based on Verilog Coding and implemented using Xilinx Software. Using the same software, test benches were constructed to verify the functionality for each of the protocols. The cache coherence protocols consist of read operations and writes operations of the cache which will be elaborated and discussed in this thesis. Based on the result, it can be seen the flow of the data transfers and the improvements of each of the protocols has brought on improving the cache system by designing a simple system that consist of a cache, a coherence protocol, and a memory. This thesis is hoped to be a help in understanding of the data transfers and coherency in cache systems and help to motivate in enhancing the current system for better performance of multi-processor. It is recommended that this design to be implemented in real life to validate the system for further development of this project. |
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