NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin

Negative Bias Temperature Instability (NBTI) is an aging mechanism that has become a key reliability issue in MOSFETs technology as well as FinFETs technology. The main reliability issues regarding the NBTI mechanism are that NBTI not only degrades the transistor electrical properties but also degra...

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Main Author:	Zainudin, Muhammad Fitri
Format:	Thesis
Language:	English
Published:	2020
Subjects:	Electric apparatus and materials Electric circuits Electric networks
Online Access:	https://ir.uitm.edu.my/id/eprint/59571/1/59571.pdf
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id	my-uitm-ir.59571
record_format	uketd_dc
spelling	my-uitm-ir.595712022-05-13T06:23:04Z NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin 2020-03 Zainudin, Muhammad Fitri Electric apparatus and materials. Electric circuits. Electric networks Negative Bias Temperature Instability (NBTI) is an aging mechanism that has become a key reliability issue in MOSFETs technology as well as FinFETs technology. The main reliability issues regarding the NBTI mechanism are that NBTI not only degrades the transistor electrical properties but also degrades the device performance as well as shortens the device operation lifetime over time. Therefore, the main objective of this study is to investigate the effect of the NBTI mechanism on the performance of the flip-flop circuits based on Single-Edge Triggered Flip-Flop (SETFF) and Double-Edge Triggered Flip-Flop (DETFF). In this work, the flip-flop circuits are simulated with different stress conditions and process variations by using HSPICE with MOSFET Reliability Analysis (MOSRA) and Predictive Technology Model (PTM) from 32nm to 16nm. The results suggested that the flip-flop circuits based on FinFET technology and MOSRA-based interface trap model (at VDD=0.85V and T=125°C) can increase the delay time by 0.026% to 4.27% while the power consumption decreases by 21.67% to 26.34%. Under the same stress conditions, the findings have shown that the performance of DETFFs has higher degradation compare to SETFFs which results in 4.27% increase in delay time and 26.34% reduction in power consumption. 2020-03 Thesis https://ir.uitm.edu.my/id/eprint/59571/ https://ir.uitm.edu.my/id/eprint/59571/1/59571.pdf text en public masters Universiti Teknologi MARA Faculty of Electrical Engineering Hussin, Hanim (Dr.) Karim, Jamilah (Dr.) Halim, Abdul Karimi
institution	Universiti Teknologi MARA
collection	UiTM Institutional Repository
language	English
advisor	Hussin, Hanim (Dr.) Karim, Jamilah (Dr.) Halim, Abdul Karimi
topic	Electric apparatus and materials Electric circuits Electric networks
spellingShingle	Electric apparatus and materials Electric circuits Electric networks Zainudin, Muhammad Fitri NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
description	Negative Bias Temperature Instability (NBTI) is an aging mechanism that has become a key reliability issue in MOSFETs technology as well as FinFETs technology. The main reliability issues regarding the NBTI mechanism are that NBTI not only degrades the transistor electrical properties but also degrades the device performance as well as shortens the device operation lifetime over time. Therefore, the main objective of this study is to investigate the effect of the NBTI mechanism on the performance of the flip-flop circuits based on Single-Edge Triggered Flip-Flop (SETFF) and Double-Edge Triggered Flip-Flop (DETFF). In this work, the flip-flop circuits are simulated with different stress conditions and process variations by using HSPICE with MOSFET Reliability Analysis (MOSRA) and Predictive Technology Model (PTM) from 32nm to 16nm. The results suggested that the flip-flop circuits based on FinFET technology and MOSRA-based interface trap model (at VDD=0.85V and T=125°C) can increase the delay time by 0.026% to 4.27% while the power consumption decreases by 21.67% to 26.34%. Under the same stress conditions, the findings have shown that the performance of DETFFs has higher degradation compare to SETFFs which results in 4.27% increase in delay time and 26.34% reduction in power consumption.
format	Thesis
qualification_level	Master's degree
author	Zainudin, Muhammad Fitri
author_facet	Zainudin, Muhammad Fitri
author_sort	Zainudin, Muhammad Fitri
title	NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
title_short	NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
title_full	NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
title_fullStr	NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
title_full_unstemmed	NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin
title_sort	nbti effects on the performance of set and det d flip-flop topologies by using mosra and predictive technology models / muhammad fitri zainudin
granting_institution	Universiti Teknologi MARA
granting_department	Faculty of Electrical Engineering
publishDate	2020
url	https://ir.uitm.edu.my/id/eprint/59571/1/59571.pdf
_version_	1783735039529320448

NBTI effects on the performance of SET and DET D flip-flop topologies by using MOSRA and predictive technology models / Muhammad Fitri Zainudin

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