Hardware design of convolutional encoder and decoder for digital communication system / Sayed Aziz Sayed Hussin
This paper focused on Convolutional Codes as one of the error detection and correction technique that use special generator polynomial. The first generator polynomial is X3 +X*+ X1 + 1 (1111) and the second generator polynomial is X3 + X2 + 1 (1011). The simulation is performing using Circuit Maker...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2003
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/68030/1/68030.pdf |
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| Summary: | This paper focused on Convolutional Codes as one of the error detection and correction technique that use special generator polynomial. The first generator polynomial is X3 +X*+ X1 + 1 (1111) and the second generator polynomial is X3 + X2 + 1 (1011). The simulation is performing using Circuit Maker for the Clock Pulse Generator to make sure the pulse is available of the D-type Flip Flop to operate. This process also is done to make sure that the pulse that we got is the suitable pulse, which is not to fast and also not too slow. The simulation process for the encoder and decoder of this hardware is perform using XILINX Designer version 2.1 toolbox to determine the process and technique of creating a digital circuit and demonstrates how the design work in encoder and decoder. This project is base on Convolution Codes including the theory, simulation technique and the hardware development of Convolutional Codes. |
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