An efficient modified booth multiplier architecture
Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth...
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| Format: | Thesis |
| Language: | English |
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| Online Access: | http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/1/full%20text.pdf http://dspace.unimap.edu.my:80/xmlui/bitstream/123456789/20815/2/p.1-24.pdf |
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| Summary: | Multiplier plays an important role in today’s compute intensive applications
such as computer graphics and digital signal processing. This thesis described the
design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between
speed and area, the design of the Modified Booth Multiplier focused on high speed with
a moderate increase in area. This was achieved by reducing the critical path delay in
the basic element of the multiplier circuit. Multiplication is performed by generating the
partial product of Modified Booth Encoding (MBE) and accumulating the entire partial
product by an adder or compressor. The research began by examining the available
encoding schemes used to generate the partial product and 4:2 compressor that are
used to accumulate the partial product. The fastest MBE and the most efficient 4:2
compressor has been used to develop the multiplier. The multiplier performance was
improved by adapting various methods such as Simplified Sign Extension (SSE) and a
proper tree topology. The SSE method eliminated some counter or adders in a partial
product row while the tree topology arrangement of the compressors and their
interconnection accumulate the partial product. A Gajski’s rule had been used to
evaluate the performance of the multiplier and the result shows that the new multiplier
has reduced delays in producing the output. The new multiplier architecture has
reduced delays to almost 2% to 7% compared to other multipliers. The high speed
multiplier was then extended to develop a Floating Point (FP) multiplier. The FP
multiplier had been successfully designed using Altera Quartus II software and
implemented on MAX EPM7182SLC84-7 device. The result showed that the FP
multiplier is 38% faster compared to conventional FP multiplier. In term of size, the FP
multiplier is 26% bigger than conventional circuit. However the increase in area of the
circuit can be tolerated since the aim was to enhance the speed of the FP Multiplier |
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