Fast fourier transform processor implementation for high inputs on field programmable gates array

In the past few years, fast Fourier transform (FFT) proved to be an efficient method to accomplish the discrete Fourier transform (DFT) with less number of operations. FFT has been vastly applied for many applications, such as image processing technique, network data transmission (XDSL, WiMAX,...

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Main Author:	Ali Abbas, Zaid
Format:	Thesis
Language:	English
Published:	2018
Subjects:	Fourier transformations Transformations (Mathematics)
Online Access:	http://psasir.upm.edu.my/id/eprint/75441/1/FK%202018%20121%20-%20IR.pdf
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spelling	my-upm-ir.754412019-11-13T07:26:13Z Fast fourier transform processor implementation for high inputs on field programmable gates array 2018-08 Ali Abbas, Zaid In the past few years, fast Fourier transform (FFT) proved to be an efficient method to accomplish the discrete Fourier transform (DFT) with less number of operations. FFT has been vastly applied for many applications, such as image processing technique, network data transmission (XDSL, WiMAX, and WLAN), orthogonal frequency-division multiplexing (OFDM), digital signal processing (DSP) and numerous applications that require high input data (1024 and up) processing. Low power and low complexity are the main concerns in high input FFT. Therefore, this research aims to investigate the power consumption, hardware resources usage and speed for radix-(2, 4 and 8) FFT processor, using the same device and environment to investigate the performance of each. Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. The results show that for the 4096 points FFT, the radix-4 is the best trade-off in term of speed, resources and power consumption, which requires only 36% of the power required by the 4069 points radix-8 FFT and 58% of the power required by the 4069 points radix-2 FFT. On another hand, for the hardware resources, the result shows that the 4096 points radix-4 FFT used 30% of hardware resources furthermore; radix-8 FFT uses approximately 45%, in the meanwhile radix-2 require 20% only. For speed, the results shows that a 4096 points radix-4 FFT is 70% faster than 4096 points radix-2 FFT and 62% slower than 4096 points radix-8 FFT. While the radix-2 may be preferred, when it comes to power saving because it only need to consume 28% less than radix-4 and 41% less than radix-8. Radix-8 is better when speed is the most important factor; it is notably 80% faster than radix-2 and 60% than radix-4. Fourier transformations Transformations (Mathematics) 2018-08 Thesis http://psasir.upm.edu.my/id/eprint/75441/ http://psasir.upm.edu.my/id/eprint/75441/1/FK%202018%20121%20-%20IR.pdf text en public masters Universiti Putra Malaysia Fourier transformations Transformations (Mathematics)
institution	Universiti Putra Malaysia
collection	PSAS Institutional Repository
language	English
topic	Fourier transformations Transformations (Mathematics)
spellingShingle	Fourier transformations Transformations (Mathematics) Ali Abbas, Zaid Fast fourier transform processor implementation for high inputs on field programmable gates array
description	In the past few years, fast Fourier transform (FFT) proved to be an efficient method to accomplish the discrete Fourier transform (DFT) with less number of operations. FFT has been vastly applied for many applications, such as image processing technique, network data transmission (XDSL, WiMAX, and WLAN), orthogonal frequency-division multiplexing (OFDM), digital signal processing (DSP) and numerous applications that require high input data (1024 and up) processing. Low power and low complexity are the main concerns in high input FFT. Therefore, this research aims to investigate the power consumption, hardware resources usage and speed for radix-(2, 4 and 8) FFT processor, using the same device and environment to investigate the performance of each. Memory-based architecture chosen to use for FFT processors, due to the reduction in the number of butterflies and rotators, as they are reused for different stages of the FFT, were implemented on Cyclone II Field Programmable Gate Arrays (FPGA). Verilog Hardware Description Language (Verilog HDL) and VHDL Languages are used to program the algorithms into the FPGA. FFT algorithms will be implemented for up to 4096 points to measure the high load processing capability. The results show that for the 4096 points FFT, the radix-4 is the best trade-off in term of speed, resources and power consumption, which requires only 36% of the power required by the 4069 points radix-8 FFT and 58% of the power required by the 4069 points radix-2 FFT. On another hand, for the hardware resources, the result shows that the 4096 points radix-4 FFT used 30% of hardware resources furthermore; radix-8 FFT uses approximately 45%, in the meanwhile radix-2 require 20% only. For speed, the results shows that a 4096 points radix-4 FFT is 70% faster than 4096 points radix-2 FFT and 62% slower than 4096 points radix-8 FFT. While the radix-2 may be preferred, when it comes to power saving because it only need to consume 28% less than radix-4 and 41% less than radix-8. Radix-8 is better when speed is the most important factor; it is notably 80% faster than radix-2 and 60% than radix-4.
format	Thesis
qualification_level	Master's degree
author	Ali Abbas, Zaid
author_facet	Ali Abbas, Zaid
author_sort	Ali Abbas, Zaid
title	Fast fourier transform processor implementation for high inputs on field programmable gates array
title_short	Fast fourier transform processor implementation for high inputs on field programmable gates array
title_full	Fast fourier transform processor implementation for high inputs on field programmable gates array
title_fullStr	Fast fourier transform processor implementation for high inputs on field programmable gates array
title_full_unstemmed	Fast fourier transform processor implementation for high inputs on field programmable gates array
title_sort	fast fourier transform processor implementation for high inputs on field programmable gates array
granting_institution	Universiti Putra Malaysia
publishDate	2018
url	http://psasir.upm.edu.my/id/eprint/75441/1/FK%202018%20121%20-%20IR.pdf
_version_	1747813051897217024

Fast fourier transform processor implementation for high inputs on field programmable gates array

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