Multi-Class Switch Architecture Designs For High Speed Packet Switching
In current communication technology, the needs of the multi-class switch have become essentials to consider traffic with different Quality-of-Service (QoS) requirements. It is crucial for the switch design to guarantee QoS for all applications. Specifically, the delay-sensitive (high priority) appli...
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my-usim-ddms-128592024-05-29T05:01:15Z Multi-Class Switch Architecture Designs For High Speed Packet Switching Abdul Aziz Bin Abdul Rahman In current communication technology, the needs of the multi-class switch have become essentials to consider traffic with different Quality-of-Service (QoS) requirements. It is crucial for the switch design to guarantee QoS for all applications. Specifically, the delay-sensitive (high priority) applications are always given preference over non-delay sensitive traffic. Previous approaches have used either absolute priority or weighted priority as their scheduler technique. However, the main weakness of their solutions is that it always serves high priority traffic. Consequently, it introduces starvation to the lower-priority traffic that may affect QoS. In this thesis, we proposed a new method known as the dual threshold setting to overcome the above limitations. Two types of buffers; input buffer and shared buffer are used throughout this thesis for testing the algorithms. The analysis is done on 16 × 16 multi-class switch with two traffic classes; the high-priority class for delay-sensitive traffic and the low-priority class. The dual thresholds' settings are used in order to improve the switch performance. This approach gives more flexibility in controlling the cell flows in the switch. This technique is further improved by introducing adaptability in the switch to cater for the problem of mean delay, which is critical for high-traffic load. The controller in the scheduler will adjust these thresholds value adaptively based on the mean queue length and traffic load condition. By adjusting these parameters adaptively the best possible mean delay and throughput for the low-priority class can be achieved without degrading the QoS requirement for high-priority class. In shared buffer switch, the problem of utilizing the buffer is crucial especially for high-traffic load. The cells will be dropped when the buffer is full. In order to minimize the cell loss of the high-class traffic in multi-class switch, a new technique to control the cell drop is introduced. Two types of threshold are used to give more flexibility in controlling the cell drops. By controlling the cell drop in the low-priority class, the high-class traffic throughput will be improved. Finally, these designs are targeted for Xilinx FPGA and tested under uniform and non-uniform traffic. The proposed methods showed that the performance of multi-class traffic improves in terms of mean delay and throughput. Universiti Sains Islam Malaysia 2013-01 Thesis en https://oarep.usim.edu.my/handle/123456789/12859 https://oarep.usim.edu.my/bitstreams/dc565c4e-b56a-4c10-8954-d179af3adf37/download 8a4605be74aa9ea9d79846c1fba20a33 Packet switching (Data transmission) Computer networks -- Management Telecommunication -- Traffic -- Management Computer network architectures |
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Packet switching (Data transmission) Computer networks -- Management Telecommunication -- Traffic -- Management Computer network architectures |
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Packet switching (Data transmission) Computer networks -- Management Telecommunication -- Traffic -- Management Computer network architectures Abdul Aziz Bin Abdul Rahman Multi-Class Switch Architecture Designs For High Speed Packet Switching |
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In current communication technology, the needs of the multi-class switch have become essentials to consider traffic with different Quality-of-Service (QoS) requirements. It is crucial for the switch design to guarantee QoS for all applications. Specifically, the delay-sensitive (high priority) applications are always given preference over non-delay sensitive traffic. Previous approaches have used either absolute priority or weighted priority as their scheduler technique. However, the main weakness of their solutions is that it always serves high priority traffic. Consequently, it introduces starvation to the lower-priority traffic that may affect QoS. In this thesis, we proposed a new method known as the dual threshold setting to overcome the above limitations. Two types of buffers; input buffer and shared buffer are used throughout this thesis for testing the algorithms. The analysis is done on 16 × 16 multi-class switch with two traffic classes; the high-priority class for delay-sensitive traffic and the low-priority class. The dual thresholds' settings are used in order to improve the switch performance. This approach gives more flexibility in controlling the cell flows in the switch. This technique is further improved by introducing adaptability in the switch to cater for the problem of mean delay, which is critical for high-traffic load. The controller in the scheduler will adjust these thresholds value adaptively based on the mean queue length and traffic load condition. By adjusting these parameters adaptively the best possible mean delay and throughput for the low-priority class can be achieved without degrading the QoS requirement for high-priority class. In shared buffer switch, the problem of utilizing the buffer is crucial especially for high-traffic load. The cells will be dropped when the buffer is full. In order to minimize the cell loss of the high-class traffic in multi-class switch, a new technique to control the cell drop is introduced. Two types of threshold are used to give more flexibility in controlling the cell drops. By controlling the cell drop in the low-priority class, the high-class traffic throughput will be improved. Finally, these designs are targeted for Xilinx FPGA and tested under uniform and non-uniform traffic. The proposed methods showed that the performance of multi-class traffic improves in terms of mean delay and throughput. |
| format |
Thesis |
| author |
Abdul Aziz Bin Abdul Rahman |
| author_facet |
Abdul Aziz Bin Abdul Rahman |
| author_sort |
Abdul Aziz Bin Abdul Rahman |
| title |
Multi-Class Switch Architecture Designs For High Speed Packet Switching |
| title_short |
Multi-Class Switch Architecture Designs For High Speed Packet Switching |
| title_full |
Multi-Class Switch Architecture Designs For High Speed Packet Switching |
| title_fullStr |
Multi-Class Switch Architecture Designs For High Speed Packet Switching |
| title_full_unstemmed |
Multi-Class Switch Architecture Designs For High Speed Packet Switching |
| title_sort |
multi-class switch architecture designs for high speed packet switching |
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Universiti Sains Islam Malaysia |
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1812444658529206272 |