Timing performance enhance for routing channel in 28NM FPGA chip
Dalam reka bentuk FPGA, saluran laluan bertindak sebagai penyambung antara kawasan dalaman dan luaran. Dengan pertumbuhan get kiraan yang semakin pantas serta rumit dalam proses nod 28nm, keperluan masa daripada reka bentuk ini adalah sukar untuk mencapai perubahan untuk semua PVT. Penganggaran masa...
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Main Author: | Kin , Si Kee |
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Format: | Thesis |
Language: | English |
Published: |
2013
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Subjects: | |
Online Access: | http://eprints.usm.my/32972/1/Kin_Si_Kee_TIMING_PERFORMANCE_ENHANCE_FOR_ROUTING_CHANNEL_IN_28NM_FPGA_CHIP__2013_MSc_E%26E_BSB_24.pdf |
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