QYPS HPS Interconnect verification methodology for SOC FPGA

FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BF...

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Main Author:	Loh , Tat Jen
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design
Online Access:	http://eprints.usm.my/32996/4/Loh_Tat_Jen_QSYS_HPS_INTERCONNECT_VERIFICATION_METHODOLOGY_FOR_SOC_FPGA_2013_MSc_E%26E_BSB_24.pdf
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spelling	my-usm-ep.329962020-10-22T03:03:22Z QYPS HPS Interconnect verification methodology for SOC FPGA 2013 Loh , Tat Jen TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BFM) sering digunakan bagi metodologi pengesahan untuk saling-sambung Qsys, HPS melibatkan protocol-protokol antaramuka yang berbeza. Tugas untuk merekabentuk dan mengesahkan BFM akan mengambil masa yang panjang. Oleh itu, metodologi pengesahan yang baru telah dicadangkan untuk saling-sambung HPS Qsys di dalam projek penyelidikan ini. Bagi kaedah pengesahan yang dicadangkan, saling-sambung HPS Qsys akan digabungkan ke dalam bangku ujian pengesahan HPS RTL melalui sejenis rekabentuk suis pin. Selain itu, rekabentuk Qsys juga digabungkan ke dalam simulasi ujian HPS RTL. Lima antaramuka Qsys, iaitu UART, SPI, FPGA-CTI, FPGA interrupt dan boot-from-FPGA telah berjaya disahkan melalui metodologi pengesahan yang dicadangkan. Berbanding dengan ujian pengesahan HPS RTL, masa simulasi yang lebih pendek telah diperhatikan semasa menguji fungsi yang sama dalam cadangan kaedah pengesahan. Field programmable gate array (FPGA) with embedded processor is the future trend for the high performance and low power applications. Qsys HPS interconnect is designed to provide seamless connection between FPGA and the embedded hard processor system (HPS) through a click of mouse. Although bus functional model (BFM) is extensively used in existing Qsys non-HPS interconnect verification methodology, HPS consists of many different interface protocols. The task of develop and validate the BFMs become the bottleneck in verification. A new Qsys HPS interconnect verification methodology has been proposed in this research project. In the proposed verification methodology, the Qsys HPS interconnect will be integrated into HPS RTL verification test bench through a pin switch architecture. Besides, the Qsys design is also integrated into HPS RTL simulation test flow. Five different Qsys interface designs, namely UART, SPI, FPGA-CTI, FPGA interrupt and boot-from-FPGA have been successfully verified using the proposed verification methodology. Shorter simulation time has been observed while testing same function in the proposed verification methodology as compared to HPS RTL verification test. 2013 Thesis http://eprints.usm.my/32996/ http://eprints.usm.my/32996/4/Loh_Tat_Jen_QSYS_HPS_INTERCONNECT_VERIFICATION_METHODOLOGY_FOR_SOC_FPGA_2013_MSc_E%26E_BSB_24.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design
spellingShingle	TK5105 Computer networks and Data transmission systems TK7868.D5 Digital electronics and Electronic circuit design Loh , Tat Jen QYPS HPS Interconnect verification methodology for SOC FPGA
description	FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BFM) sering digunakan bagi metodologi pengesahan untuk saling-sambung Qsys, HPS melibatkan protocol-protokol antaramuka yang berbeza. Tugas untuk merekabentuk dan mengesahkan BFM akan mengambil masa yang panjang. Oleh itu, metodologi pengesahan yang baru telah dicadangkan untuk saling-sambung HPS Qsys di dalam projek penyelidikan ini. Bagi kaedah pengesahan yang dicadangkan, saling-sambung HPS Qsys akan digabungkan ke dalam bangku ujian pengesahan HPS RTL melalui sejenis rekabentuk suis pin. Selain itu, rekabentuk Qsys juga digabungkan ke dalam simulasi ujian HPS RTL. Lima antaramuka Qsys, iaitu UART, SPI, FPGA-CTI, FPGA interrupt dan boot-from-FPGA telah berjaya disahkan melalui metodologi pengesahan yang dicadangkan. Berbanding dengan ujian pengesahan HPS RTL, masa simulasi yang lebih pendek telah diperhatikan semasa menguji fungsi yang sama dalam cadangan kaedah pengesahan. Field programmable gate array (FPGA) with embedded processor is the future trend for the high performance and low power applications. Qsys HPS interconnect is designed to provide seamless connection between FPGA and the embedded hard processor system (HPS) through a click of mouse. Although bus functional model (BFM) is extensively used in existing Qsys non-HPS interconnect verification methodology, HPS consists of many different interface protocols. The task of develop and validate the BFMs become the bottleneck in verification. A new Qsys HPS interconnect verification methodology has been proposed in this research project. In the proposed verification methodology, the Qsys HPS interconnect will be integrated into HPS RTL verification test bench through a pin switch architecture. Besides, the Qsys design is also integrated into HPS RTL simulation test flow. Five different Qsys interface designs, namely UART, SPI, FPGA-CTI, FPGA interrupt and boot-from-FPGA have been successfully verified using the proposed verification methodology. Shorter simulation time has been observed while testing same function in the proposed verification methodology as compared to HPS RTL verification test.
format	Thesis
qualification_level	Master's degree
author	Loh , Tat Jen
author_facet	Loh , Tat Jen
author_sort	Loh , Tat Jen
title	QYPS HPS Interconnect verification methodology for SOC FPGA
title_short	QYPS HPS Interconnect verification methodology for SOC FPGA
title_full	QYPS HPS Interconnect verification methodology for SOC FPGA
title_fullStr	QYPS HPS Interconnect verification methodology for SOC FPGA
title_full_unstemmed	QYPS HPS Interconnect verification methodology for SOC FPGA
title_sort	qyps hps interconnect verification methodology for soc fpga
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2013
url	http://eprints.usm.my/32996/4/Loh_Tat_Jen_QSYS_HPS_INTERCONNECT_VERIFICATION_METHODOLOGY_FOR_SOC_FPGA_2013_MSc_E%26E_BSB_24.pdf
_version_	1747820576535216128

QYPS HPS Interconnect verification methodology for SOC FPGA

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