QYPS HPS Interconnect verification methodology for SOC FPGA
FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BF...
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Main Author: | Loh , Tat Jen |
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Format: | Thesis |
Language: | English |
Published: |
2013
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Subjects: | |
Online Access: | http://eprints.usm.my/32996/4/Loh_Tat_Jen_QSYS_HPS_INTERCONNECT_VERIFICATION_METHODOLOGY_FOR_SOC_FPGA_2013_MSc_E%26E_BSB_24.pdf |
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