Design Optimization Of Datapath Transmitter In Bluetooth Baseband Controller
A Bluetooth baseband controller is placed in the physical layer of the Bluetooth Protocol stack to manage all the physical channels and links like error correction, hop selection, security and data whitening. The baseband handles the packets and does the inquiry for the Bluetooth devices in the area...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2017
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| Subjects: | |
| Online Access: | http://eprints.usm.my/39417/1/LIM_HWEI_EAN_24_Pages.pdf |
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| Summary: | A Bluetooth baseband controller is placed in the physical layer of the Bluetooth Protocol stack to manage all the physical channels and links like error correction, hop selection, security and data whitening. The baseband handles the packets and does the inquiry for the Bluetooth devices in the area. The optimization of the performance is needed but it is of a trade off with the area and power consumption of the device. The bigger the design, the more the power being consumed. In this thesis, the objective is to optimize the design of the transmitter in the datapath of the Bluetooth baseband controller. It is also part of the objective to improve the RC delay of the worst path timing. The inherited codes need to be verified with a test bench on Model Sim first. Then, a synthesis process is being done using the Synopsys tool in order to generate a netlist. The netlist is then being translated into physical implementation of the logic and the layout is formed. Then, the optimization process starts again from the VHDL code to the layout process. The synthesized results are first being compared with the results from the IC Compiler. The results of the synthesized results before and after optimization is being compared as well. It is shown that the optimized design has a larger area and power consumption of 75023.627147 square micron and 18.2595 mW but the timing in the worst path is significantly improved from 4 ps to 390 ps. The transmitter is able to operate at 200 MHz from the constraint set and the operating voltage is at 1.62 V. Thus, a tradeoff with the area and power consumption is in place if optimization on the timing performance is done. The focus of this project is on the performance of the design. |
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