Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especial for low-cost device. One of the major factor of test cost contributed is the test time. For the low-cost product...

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Main Author:	Kesavan Prabagaran, Premkumar
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/39561/1/PREMKUMAR_AL_KESAVAN_PRABAGARAN-24_Pages.pdf
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id	my-usm-ep.39561
record_format	uketd_dc
spelling	my-usm-ep.395612019-04-12T05:25:05Z Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment 2017 Kesavan Prabagaran, Premkumar TK1-9971 Electrical engineering. Electronics. Nuclear engineering Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especial for low-cost device. One of the major factor of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithm have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this examples, approximate 33% of test time reduction observed for 1Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow. 2017 Thesis http://eprints.usm.my/39561/ http://eprints.usm.my/39561/1/PREMKUMAR_AL_KESAVAN_PRABAGARAN-24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Kesavan Prabagaran, Premkumar Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
description	Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especial for low-cost device. One of the major factor of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithm have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this examples, approximate 33% of test time reduction observed for 1Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.
format	Thesis
qualification_level	Master's degree
author	Kesavan Prabagaran, Premkumar
author_facet	Kesavan Prabagaran, Premkumar
author_sort	Kesavan Prabagaran, Premkumar
title	Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
title_short	Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
title_full	Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
title_fullStr	Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
title_full_unstemmed	Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment
title_sort	optimizing ram testing method for test time saving using automatic test equipment
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2017
url	http://eprints.usm.my/39561/1/PREMKUMAR_AL_KESAVAN_PRABAGARAN-24_Pages.pdf
_version_	1747820759391141888

Optimizing Ram Testing Method For Test Time Saving Using Automatic Test Equipment

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