Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana...
Saved in:
Main Author: | Chew , Ming Choo |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://eprints.usm.my/40694/1/Design_Of_Fpga_Address_Register_In_28nm_Process_Technology_Based_On_Standard_Cell_Based_Approach.pdf |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Technique Of Pvt Analysis On Sd Controller Timing Validation For 28nm Soc Fpga
by: Yusni, Nur Amalina Aiza
Published: (2015) -
Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
by: Wan Ismail, Wan Mohd Fahmi
Published: (2015) -
Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via
K-Nearest Centroid Neighbors
by: Yew , Tze Ee
Published: (2016) -
Development Of QRS Detection Algoritm For FPGA Implementation
by: Ong, Seng Hooi
Published: (2003) -
Hybrid Diagnosis Model To Determine Fault Isolation For Scan Chain Failure Analysis On 22nm Fabrication Process
by: Victor Paulraj, Eric Paulraj
Published: (2016)