Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology

Unit Aritmetik Logik (ALU) adalah litar digital dan ia digunakan untuk melaksanakan semua operasi aritmetik dan operasi logik. Selain itu penambah adalah bahagian yang paling penting di kalangan ALU kerana ia telah digunakan dalam operasi aritmetik lain. Sekarang terdapat tiga parameter prestasi uta...

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Main Author: Lim, Nguk Jie
Format: Thesis
Language:English
Published: 2015
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Online Access:http://eprints.usm.my/40706/1/Design_and_Implementation_of_Low_Power_and_High_Performance_4_Bit_Carry_Lookahead_Full_Adder_Using_Finfet_Technology.pdf
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spelling my-usm-ep.407062018-06-06T07:08:15Z Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology 2015-08 Lim, Nguk Jie T Technology TK7800-8360 Electronics Unit Aritmetik Logik (ALU) adalah litar digital dan ia digunakan untuk melaksanakan semua operasi aritmetik dan operasi logik. Selain itu penambah adalah bahagian yang paling penting di kalangan ALU kerana ia telah digunakan dalam operasi aritmetik lain. Sekarang terdapat tiga parameter prestasi utama iaitu Dimensi, Kelajuan dan Kuasa tertumpu oleh pereka VLSI untuk penambahbaikan reka bentuk mereka. Maka, peningkatan kelajuan di penambah akan mempercepatkan pelaksanaan semua operasi aritmetik lain. Penambah Bawa Lihat Ke Depan (CLA) telah dipilih kerana ia mempercepatkan pengiraan dengan mengurangkan jumlah masa dalam penentuan bit untuk menjalankan operasi penambahan dengan lebih cepat. 4-bit CLA boleh dilaksanakan dengan pelbagai jenis transistor, seperti FinFet dan Transistor Kesan Medan Separuh Pengalir Oksida Logam (MOSFET). Di project ini, CLA yang menggunakan teknologi 14nm FinFET dalam Penghantaran Pintu (TG) telah mengesahkan kebolehan teknologi baru ini di dalam reka bentuk penambah penuh terdapat pengurangan kira-kira 52% dalam nilai parameter pelesapan kuasa berbanding teknik 22nm CMOS. Kesimpulannya, ia telah menunjukkan bahawa litar CLA yang dicadangkan dalam 14nm FinFET dalam TG dapat menyediakan kelajuan yang lebih baik dengan kuasa pelesapan-kurangnya berbanding dengan kerja-kerja sebelumnya. ________________________________________________________________________________________________________________________ An Arithmetic Logic Unit (ALU) is a digital circuit and used to perform all arithmetic operations and logic operations. Addition is the most important part among of the ALU since it has been used in other arithmetic operation. Now there are three main performance parameters i.e. area, speed and power are focused by VLSI designer to optimize their design. Therefore, improving the speed of addition increase the performance of all other arithmetic operations. The Carry Look-Ahead Adder (CLA) has been chosen because it speeds up the carry computation by reducing the amount of time to determine carry bits. The 4-bit CLA Full Adder can be implemented with different types of transistor, such as FinFET and Metal Oxide Semiconductor Field-Effect Transistor (MOSFET), which may have difference performance in supply voltage variation. In this project, the analysis of the simulated results confirm the feasibility of the 14nm FinFET techniques in Transmission Gate (TG) style full adder design and shows that there is reduction of approximately 52% in the value of power dissipation parameter as compared to CMOS 22nm technique. In conclusion, it has been shown that the proposed CLA circuit in 14nm FinFET in TG provides better speed with the least power dissipation compared to the previous works. 2015-08 Thesis http://eprints.usm.my/40706/ http://eprints.usm.my/40706/1/Design_and_Implementation_of_Low_Power_and_High_Performance_4_Bit_Carry_Lookahead_Full_Adder_Using_Finfet_Technology.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik Dan Elektronik
institution Universiti Sains Malaysia
collection USM Institutional Repository
language English
topic T Technology
TK7800-8360 Electronics
spellingShingle T Technology
TK7800-8360 Electronics
Lim, Nguk Jie
Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
description Unit Aritmetik Logik (ALU) adalah litar digital dan ia digunakan untuk melaksanakan semua operasi aritmetik dan operasi logik. Selain itu penambah adalah bahagian yang paling penting di kalangan ALU kerana ia telah digunakan dalam operasi aritmetik lain. Sekarang terdapat tiga parameter prestasi utama iaitu Dimensi, Kelajuan dan Kuasa tertumpu oleh pereka VLSI untuk penambahbaikan reka bentuk mereka. Maka, peningkatan kelajuan di penambah akan mempercepatkan pelaksanaan semua operasi aritmetik lain. Penambah Bawa Lihat Ke Depan (CLA) telah dipilih kerana ia mempercepatkan pengiraan dengan mengurangkan jumlah masa dalam penentuan bit untuk menjalankan operasi penambahan dengan lebih cepat. 4-bit CLA boleh dilaksanakan dengan pelbagai jenis transistor, seperti FinFet dan Transistor Kesan Medan Separuh Pengalir Oksida Logam (MOSFET). Di project ini, CLA yang menggunakan teknologi 14nm FinFET dalam Penghantaran Pintu (TG) telah mengesahkan kebolehan teknologi baru ini di dalam reka bentuk penambah penuh terdapat pengurangan kira-kira 52% dalam nilai parameter pelesapan kuasa berbanding teknik 22nm CMOS. Kesimpulannya, ia telah menunjukkan bahawa litar CLA yang dicadangkan dalam 14nm FinFET dalam TG dapat menyediakan kelajuan yang lebih baik dengan kuasa pelesapan-kurangnya berbanding dengan kerja-kerja sebelumnya. ________________________________________________________________________________________________________________________ An Arithmetic Logic Unit (ALU) is a digital circuit and used to perform all arithmetic operations and logic operations. Addition is the most important part among of the ALU since it has been used in other arithmetic operation. Now there are three main performance parameters i.e. area, speed and power are focused by VLSI designer to optimize their design. Therefore, improving the speed of addition increase the performance of all other arithmetic operations. The Carry Look-Ahead Adder (CLA) has been chosen because it speeds up the carry computation by reducing the amount of time to determine carry bits. The 4-bit CLA Full Adder can be implemented with different types of transistor, such as FinFET and Metal Oxide Semiconductor Field-Effect Transistor (MOSFET), which may have difference performance in supply voltage variation. In this project, the analysis of the simulated results confirm the feasibility of the 14nm FinFET techniques in Transmission Gate (TG) style full adder design and shows that there is reduction of approximately 52% in the value of power dissipation parameter as compared to CMOS 22nm technique. In conclusion, it has been shown that the proposed CLA circuit in 14nm FinFET in TG provides better speed with the least power dissipation compared to the previous works.
format Thesis
qualification_level Master's degree
author Lim, Nguk Jie
author_facet Lim, Nguk Jie
author_sort Lim, Nguk Jie
title Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
title_short Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
title_full Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
title_fullStr Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
title_full_unstemmed Design and Implementation of Low Power and High Performance 4 Bit Carry Lookahead Full Adder Using Finfet Technology
title_sort design and implementation of low power and high performance 4 bit carry lookahead full adder using finfet technology
granting_institution Universiti Sains Malaysia
granting_department Pusat Pengajian Kejuruteraan Elektrik Dan Elektronik
publishDate 2015
url http://eprints.usm.my/40706/1/Design_and_Implementation_of_Low_Power_and_High_Performance_4_Bit_Carry_Lookahead_Full_Adder_Using_Finfet_Technology.pdf
_version_ 1747820806693453824