Partial Binary Tree Network (Pbtn): A New Dynamic Element Matching (Dem) Approach To Current Steering Digital Analog Converter (Dac)
DACs are essential operations in many digital system which required high performance data converters. With shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures highly relying on matched components to perform data converters. Howeve...
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| Format: | Thesis |
| Language: | English |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://eprints.usm.my/40939/1/TEH_CHOON_YAN_24_pages.pdf |
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| Summary: | DACs are essential operations in many digital system which required high performance data converters. With shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures highly relying on matched components to perform data converters. However, components matched are nearly impossible to fabricate, there are always mismatch errors which caused the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. With this technique, the time averages of the equivalent components at each of the component positions are equal or nearly equal to reduce the effects of component differences in electronic circuits. The drawback of existing works is DAC would suffer from excessive digital hardware complexity. A complicated encoding is usually necessary for conventional DEM encoders which will lead to a lot of switch transitions at the same time and it will bring glitches to the output signal. In this research, a new DEM algorithm is proposed on Current-Steering DACs with Partial Binary Tree Network (PBTN) algorithm to overcome glitches transitions with low complexity. The analysis related to the performance of DAC such as glitch impulse areas, Integral Nonlinearity (INL), Differential Nonlinearity (DNL) and power consumption are shown to be equivalent and have at least 56% hardware efficient implementations compared to exiting DEM algorithm.
Simulation results for 3-bit and 4-bit PBTN compared with 3-bit and 4-bit conventional Binary Tree Network (BTN) show that both algorithms are equivalent in performance with DNL and INL errors of +/- 0.2 LSB and the proposed algorithm has even lower power consumption due to small amount of transmission gates used. Simulation results for 8-bit PBTN with 1MSB randomization achieved INL of 1.5385 LSB and DNL 0.2605 LSB with power consumption of 22.2 mW. Besides that, PBTN algorithm provides the flexibility to improve the DAC performance by increasing numbers of randomization implementation on MSB. |
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