New Cdc Design Tool For Analog Layout Workflow
The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ t...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.usm.my/40966/1/NG_HIN_MUNG_24_pages.pdf |
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| Summary: | The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ time in previous project cycle according to the complexity of the circuit. In the meantime, designer needs to convert the devices from schematic into layout in canvas of layout editor, and then arrange the devices accordingly one by one or group by group by moving the devices in order to complete device placement. While for routing, even though there are different auto-routers in existing layout editing tool, but these routers are mostly developed for digital design and unable to route analog signals precisely especially when there are constraints for the routing like matching and shielding. This research presents a new automation solution, Cartoon Diagram Compiler (CDC) tool that enabling a significant productivity improvement on analog layout design. The automation tool provides capability to drag-and-drop the transistor devices/instance cells from schematics canvas to floor planning canvas and is able to auto-place non-critical cells and devices in a virtual mode before converting into real layout. After the floorplan/placement fulfill the design requirement, topologies generator can be used for quick preview of routing option and auto-router support for constrained (shield critical net) and un-constrained nets routing. The area and routing quality nearly matched with hand-drawn layout. The CDC tool has been compare and evaluated on Intel in-house analog layout design projects. In research evaluation, the average time to complete manual device placement and layout routing required 640 minutes and 554 minutes respectively. With device placement and layout routing process only required 139 minutes and 112 minutes or significant reduction in period of about 5.14x and 6.31x respectively. In conclusion, CDC tool increases the productivity by allowing fully automatic derivation of placement and routing, incremental design updates and smart placement guaranteeing design rule free from violation. |
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