Functional Verification Test Time Reduction Through Behavioral Functional Model
Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases t...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://eprints.usm.my/41112/1/Lee_Chee_Keng_24_Pages.pdf |
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| Summary: | Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases the verification lead time which will then lead to potential failure of the design to meet market on time. One of the key factor in slowing down the design verification flow is the long simulation time during the pre-silicon functional testing. The long test simulation time issue is seen in NAND Intellectual Property (IP) pre-silicon validation. Therefore in this project, a behavioral Bus Functional Model (BFM) is implemented for NAND IP to improve the test simulation time. The BFM has been successfully implemented to validate NAND IP. Simulation of test with similar functional testing scenarios have been exercised on NAND IP in existing verification environment and in verification environment with BFM integrated. As a result, the BFM is found to have behaved accurately comparing with the existing functional Register Transfer Level (RTL) to validate NAND IP. Comparison has also shown the test simulation time through the environment with BFM integrated using Verilog Compiler Simulator (VCS) had shown significant average improvement of 92.8%. Therefore the implemented BFM is justified to be a suitable use on NAND IP validation. |
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