Functional Verification Test Time Reduction Through Behavioral Functional Model

Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases t...

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Main Author:	Lee , Chee Keng
Format:	Thesis
Language:	English
Published:	2014
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41112/1/Lee_Chee_Keng_24_Pages.pdf
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id	my-usm-ep.41112
record_format	uketd_dc
spelling	my-usm-ep.411122018-07-19T08:29:11Z Functional Verification Test Time Reduction Through Behavioral Functional Model 2014 Lee , Chee Keng TK7800-8360 Electronics Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases the verification lead time which will then lead to potential failure of the design to meet market on time. One of the key factor in slowing down the design verification flow is the long simulation time during the pre-silicon functional testing. The long test simulation time issue is seen in NAND Intellectual Property (IP) pre-silicon validation. Therefore in this project, a behavioral Bus Functional Model (BFM) is implemented for NAND IP to improve the test simulation time. The BFM has been successfully implemented to validate NAND IP. Simulation of test with similar functional testing scenarios have been exercised on NAND IP in existing verification environment and in verification environment with BFM integrated. As a result, the BFM is found to have behaved accurately comparing with the existing functional Register Transfer Level (RTL) to validate NAND IP. Comparison has also shown the test simulation time through the environment with BFM integrated using Verilog Compiler Simulator (VCS) had shown significant average improvement of 92.8%. Therefore the implemented BFM is justified to be a suitable use on NAND IP validation. 2014 Thesis http://eprints.usm.my/41112/ http://eprints.usm.my/41112/1/Lee_Chee_Keng_24_Pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Lee , Chee Keng Functional Verification Test Time Reduction Through Behavioral Functional Model
description	Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases the verification lead time which will then lead to potential failure of the design to meet market on time. One of the key factor in slowing down the design verification flow is the long simulation time during the pre-silicon functional testing. The long test simulation time issue is seen in NAND Intellectual Property (IP) pre-silicon validation. Therefore in this project, a behavioral Bus Functional Model (BFM) is implemented for NAND IP to improve the test simulation time. The BFM has been successfully implemented to validate NAND IP. Simulation of test with similar functional testing scenarios have been exercised on NAND IP in existing verification environment and in verification environment with BFM integrated. As a result, the BFM is found to have behaved accurately comparing with the existing functional Register Transfer Level (RTL) to validate NAND IP. Comparison has also shown the test simulation time through the environment with BFM integrated using Verilog Compiler Simulator (VCS) had shown significant average improvement of 92.8%. Therefore the implemented BFM is justified to be a suitable use on NAND IP validation.
format	Thesis
qualification_level	Master's degree
author	Lee , Chee Keng
author_facet	Lee , Chee Keng
author_sort	Lee , Chee Keng
title	Functional Verification Test Time Reduction Through Behavioral Functional Model
title_short	Functional Verification Test Time Reduction Through Behavioral Functional Model
title_full	Functional Verification Test Time Reduction Through Behavioral Functional Model
title_fullStr	Functional Verification Test Time Reduction Through Behavioral Functional Model
title_full_unstemmed	Functional Verification Test Time Reduction Through Behavioral Functional Model
title_sort	functional verification test time reduction through behavioral functional model
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2014
url	http://eprints.usm.my/41112/1/Lee_Chee_Keng_24_Pages.pdf
_version_	1747820877044514816

Functional Verification Test Time Reduction Through Behavioral Functional Model

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