Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis

As the size of transistor is shrinking, the difficulty of a design to meet timing has increased. Also, continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification...

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Main Author:	Ong, Chun Kiat
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/45189/1/Ong%20Chun%20Kiat24.pdf
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id	my-usm-ep.45189
record_format	uketd_dc
spelling	my-usm-ep.451892019-08-05T03:32:47Z Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis 2013-07 Ong, Chun Kiat TK1-9971 Electrical engineering. Electronics. Nuclear engineering As the size of transistor is shrinking, the difficulty of a design to meet timing has increased. Also, continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV) process or Static Timing Analysis (STA) tool is unable to cover the timing verification of asynchronous based design, asynchronous design is changed to synchronous based for the STA tools to ensure the silicon timing can be met across various PVT. Synchronous design is a design where the transaction of data is governed by clock whereas asynchronous is a design where the transaction of data is event based which is not based on clock. Intel 8254 Programmable Interval Timer (PIT) which is an asynchronous based design is used as a case study in this research. A design flow which included the asynchronous path identification and technique implementation from asynchronous to synchronous without functionality changes has been proposed. Techniques conversion from asynchronous to synchronous including the clock placement, delays, combinational loop, latch, clock domain crossing, and reset are implemented on the 8254 PIT. The functionality of the synchronous 8254 PIT is validated with total of 22 test cases. Result shows the timing analysis coverage of 8254 PIT by STA has been increased from 40% in asynchronous design based to 91% in synchronous design based. The timing analysis coverage of new synchronous 8254 PIT will be 100% if excluding the asynchronous reset path. 2013-07 Thesis http://eprints.usm.my/45189/ http://eprints.usm.my/45189/1/Ong%20Chun%20Kiat24.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Ong, Chun Kiat Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
description	As the size of transistor is shrinking, the difficulty of a design to meet timing has increased. Also, continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV) process or Static Timing Analysis (STA) tool is unable to cover the timing verification of asynchronous based design, asynchronous design is changed to synchronous based for the STA tools to ensure the silicon timing can be met across various PVT. Synchronous design is a design where the transaction of data is governed by clock whereas asynchronous is a design where the transaction of data is event based which is not based on clock. Intel 8254 Programmable Interval Timer (PIT) which is an asynchronous based design is used as a case study in this research. A design flow which included the asynchronous path identification and technique implementation from asynchronous to synchronous without functionality changes has been proposed. Techniques conversion from asynchronous to synchronous including the clock placement, delays, combinational loop, latch, clock domain crossing, and reset are implemented on the 8254 PIT. The functionality of the synchronous 8254 PIT is validated with total of 22 test cases. Result shows the timing analysis coverage of 8254 PIT by STA has been increased from 40% in asynchronous design based to 91% in synchronous design based. The timing analysis coverage of new synchronous 8254 PIT will be 100% if excluding the asynchronous reset path.
format	Thesis
qualification_level	Master's degree
author	Ong, Chun Kiat
author_facet	Ong, Chun Kiat
author_sort	Ong, Chun Kiat
title	Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
title_short	Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
title_full	Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
title_fullStr	Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
title_full_unstemmed	Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis
title_sort	migration from asynchronous to synchronous 8254 programmable interval timer for effective static timing analysis
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik & Elektronik
publishDate	2013
url	http://eprints.usm.my/45189/1/Ong%20Chun%20Kiat24.pdf
_version_	1747821465160384512

Migration From Asynchronous To Synchronous 8254 Programmable Interval Timer For Effective Static Timing Analysis

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