BinDCT Design and Implementation on FPGA with Low Power Architecture

Image compression is widely used in today's consumer applications such as digital camcorders, digital cameras, videophones and high-definition television (HDTV). As Discrete Cosine Transform (DCT) is dominant in many international standards for image/video and audio compression, the introductio...

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Main Author:	Jabbar, Mohamad Hairol
Format:	Thesis
Language:	English
Published:	2008
Subjects:	TA1501-1820 Applied optics Photonics
Online Access:	http://eprints.uthm.edu.my/2217/1/Mohamad%20Hairol%20Jabbar%20-%2024p.pdf
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id	my-uthm-ep.2217
record_format	uketd_dc
spelling	my-uthm-ep.22172021-10-31T04:33:45Z BinDCT Design and Implementation on FPGA with Low Power Architecture 2008-09 Jabbar, Mohamad Hairol TA1501-1820 Applied optics. Photonics Image compression is widely used in today's consumer applications such as digital camcorders, digital cameras, videophones and high-definition television (HDTV). As Discrete Cosine Transform (DCT) is dominant in many international standards for image/video and audio compression, the introduction of multiplierless algorithm for fast DCT computation known as BinDCT (Binary DCT) is very well suited for VLSI implementation. Its performances in term of Peak Signal-to-Noise (PSNR), compression ratio and coding gain is proved to be best approximation to the DCT algorithm. In this work, the design and implementation of 8 x 8 block 2-D forward BinDCT algorithm on a Field Programmable Gate Array (FPGA) is presented. As this algorithm uses simple arithmetic operations (shift and add) rather than floating-point multiplications, low power hardware implementation is very promising. The aim for low power implementation was achieved at architectural level by employing 4 stages pipeline architecture with parallel processing in each stage. However, due to the trade off between hardware area and speed, this design is focusing on optimising hardware area in each stage such that it can fit the target FPGA device. The 8 x 8 block two-dimensional (2-D) forward BinDCT implementation can be run at 68.58 MHz with the power consumption of 144.10 mW. This implementation achieved 12.45% less power compare with the implementation of BinDCT presented previously if the design runs at the same speed. Furthermore, results have shown that this implementation achieved good accuracy compare with software implementation as the maximum error of the output from 2-D computation is 1.26 %. Several works can be done for further power optimisation such as data gating and latency balancing at each stage (which can improves the throughput as well). Besides, the implementation of 8 x 8 block 2-D inverse BinDCT should be carried out such that its accuracy over floating-point DCT in terms of hardware implementation can be analyzed. 2008-09 Thesis http://eprints.uthm.edu.my/2217/ http://eprints.uthm.edu.my/2217/1/Mohamad%20Hairol%20Jabbar%20-%2024p.pdf text en public mphil masters Liverpool John Moores University Faculty of Engineering Technology
institution	Universiti Tun Hussein Onn Malaysia
collection	UTHM Institutional Repository
language	English
topic	TA1501-1820 Applied optics Photonics
spellingShingle	TA1501-1820 Applied optics Photonics Jabbar, Mohamad Hairol BinDCT Design and Implementation on FPGA with Low Power Architecture
description	Image compression is widely used in today's consumer applications such as digital camcorders, digital cameras, videophones and high-definition television (HDTV). As Discrete Cosine Transform (DCT) is dominant in many international standards for image/video and audio compression, the introduction of multiplierless algorithm for fast DCT computation known as BinDCT (Binary DCT) is very well suited for VLSI implementation. Its performances in term of Peak Signal-to-Noise (PSNR), compression ratio and coding gain is proved to be best approximation to the DCT algorithm. In this work, the design and implementation of 8 x 8 block 2-D forward BinDCT algorithm on a Field Programmable Gate Array (FPGA) is presented. As this algorithm uses simple arithmetic operations (shift and add) rather than floating-point multiplications, low power hardware implementation is very promising. The aim for low power implementation was achieved at architectural level by employing 4 stages pipeline architecture with parallel processing in each stage. However, due to the trade off between hardware area and speed, this design is focusing on optimising hardware area in each stage such that it can fit the target FPGA device. The 8 x 8 block two-dimensional (2-D) forward BinDCT implementation can be run at 68.58 MHz with the power consumption of 144.10 mW. This implementation achieved 12.45% less power compare with the implementation of BinDCT presented previously if the design runs at the same speed. Furthermore, results have shown that this implementation achieved good accuracy compare with software implementation as the maximum error of the output from 2-D computation is 1.26 %. Several works can be done for further power optimisation such as data gating and latency balancing at each stage (which can improves the throughput as well). Besides, the implementation of 8 x 8 block 2-D inverse BinDCT should be carried out such that its accuracy over floating-point DCT in terms of hardware implementation can be analyzed.
format	Thesis
qualification_name	Master of Philosophy (M.Phil.)
qualification_level	Master's degree
author	Jabbar, Mohamad Hairol
author_facet	Jabbar, Mohamad Hairol
author_sort	Jabbar, Mohamad Hairol
title	BinDCT Design and Implementation on FPGA with Low Power Architecture
title_short	BinDCT Design and Implementation on FPGA with Low Power Architecture
title_full	BinDCT Design and Implementation on FPGA with Low Power Architecture
title_fullStr	BinDCT Design and Implementation on FPGA with Low Power Architecture
title_full_unstemmed	BinDCT Design and Implementation on FPGA with Low Power Architecture
title_sort	bindct design and implementation on fpga with low power architecture
granting_institution	Liverpool John Moores University
granting_department	Faculty of Engineering Technology
publishDate	2008
url	http://eprints.uthm.edu.my/2217/1/Mohamad%20Hairol%20Jabbar%20-%2024p.pdf
_version_	1747830926243528704

BinDCT Design and Implementation on FPGA with Low Power Architecture

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