APA引文

Lee, S. J. (2018). Design of low power high speed digital vedic multiplier using 13T hybrid full adder.

Chicago Style (17th ed.) Citation

Lee, Shing Jie. Design of Low Power High Speed Digital Vedic Multiplier Using 13T Hybrid Full Adder. 2018.

MLA引文

Lee, Shing Jie. Design of Low Power High Speed Digital Vedic Multiplier Using 13T Hybrid Full Adder. 2018.

警告：這些引文格式不一定是100％准確.