Design of low power high speed digital vedic multiplier using 13T hybrid full adder
The increment of demand for battery operated portable devices has laid emphasis on the development of low power multiplier and high performance systems. Multiplier is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had di...
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| 格式: | Thesis |
| 語言: | English English English |
| 出版: |
2018
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| 在線閱讀: | http://eprints.uthm.edu.my/428/1/24p%20LEE%20SHING%20JEE.pdf http://eprints.uthm.edu.my/428/2/LEE%20SHING%20JIE%20COPYRIGHT%20DECLARATION.pdf http://eprints.uthm.edu.my/428/3/LEE%20SHING%20JIE%20WATERMARK.pdf |
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