Single phase asymmetrical multilevel inverter topology with reduced device count

Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications. However, the number of components will increase with increased output voltage levels. It leads to high power losses. In this thesis, a new single-phase asymmetrical multilevel inverter topology used for...

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Main Author:	Arif, M. Saad
Format:	Thesis
Language:	English
Published:	2022
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/101913/1/MSaadArifPSKE2022.pdf
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spelling	my-utm-ep.1019132023-07-22T03:58:17Z Single phase asymmetrical multilevel inverter topology with reduced device count 2022 Arif, M. Saad TK Electrical engineering. Electronics Nuclear engineering Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications. However, the number of components will increase with increased output voltage levels. It leads to high power losses. In this thesis, a new single-phase asymmetrical multilevel inverter topology used for medium and high voltage applications is proposed. The topology is capable of producing n-level output voltage with reduced device counts. It is achieved by arranging available switches and direct current (dc)-sources to obtain the maximum combinations of addition and subtraction of the input dc-sources. A comprehensive literature review has been carried out, and the proposed topology is compared with the topologies available in the literature. Comparison based on the number of switches utilized, the number of dc sources used, and the total number of devices is made. To verify the viability of the proposed topology, circuit models for 9-level, 25-level, and 67-level inverters are developed and simulated in Matlab-Simulink software first. Voltage and current waveforms and THD for resistive and inductive loads are obtained from the simulation model and validated with the experimental setup. Experimental results of the proposed inverter prototype for 9-level and 25-level output, developed in the laboratory, are presented. A low-frequency and high-frequency switching strategy for the proposed inverter topology are also presented in this work. Thermal modelling of the proposed topology is done in PLECS software, and detailed loss analysis for 9-level as well as 25-level topologies is carried out. The fundamental topology utilizes 9 switches with a total standing voltage (TSV) of 6.75 per unit while the 25-level topology structure has 12 switches with the TSV of 6.92 per unit only. Comparison with the other multilevel topologies shows that the proposed circuit requires fewer power switches and dc-sources to produce the same output levels. Due to the low switching frequency requirement, the proposed topology is applicable for high and medium voltage applications, resulting in lower switching losses. 2022 Thesis http://eprints.utm.my/id/eprint/101913/ http://eprints.utm.my/id/eprint/101913/1/MSaadArifPSKE2022.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149147 phd doctoral Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Arif, M. Saad Single phase asymmetrical multilevel inverter topology with reduced device count
description	Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications. However, the number of components will increase with increased output voltage levels. It leads to high power losses. In this thesis, a new single-phase asymmetrical multilevel inverter topology used for medium and high voltage applications is proposed. The topology is capable of producing n-level output voltage with reduced device counts. It is achieved by arranging available switches and direct current (dc)-sources to obtain the maximum combinations of addition and subtraction of the input dc-sources. A comprehensive literature review has been carried out, and the proposed topology is compared with the topologies available in the literature. Comparison based on the number of switches utilized, the number of dc sources used, and the total number of devices is made. To verify the viability of the proposed topology, circuit models for 9-level, 25-level, and 67-level inverters are developed and simulated in Matlab-Simulink software first. Voltage and current waveforms and THD for resistive and inductive loads are obtained from the simulation model and validated with the experimental setup. Experimental results of the proposed inverter prototype for 9-level and 25-level output, developed in the laboratory, are presented. A low-frequency and high-frequency switching strategy for the proposed inverter topology are also presented in this work. Thermal modelling of the proposed topology is done in PLECS software, and detailed loss analysis for 9-level as well as 25-level topologies is carried out. The fundamental topology utilizes 9 switches with a total standing voltage (TSV) of 6.75 per unit while the 25-level topology structure has 12 switches with the TSV of 6.92 per unit only. Comparison with the other multilevel topologies shows that the proposed circuit requires fewer power switches and dc-sources to produce the same output levels. Due to the low switching frequency requirement, the proposed topology is applicable for high and medium voltage applications, resulting in lower switching losses.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Arif, M. Saad
author_facet	Arif, M. Saad
author_sort	Arif, M. Saad
title	Single phase asymmetrical multilevel inverter topology with reduced device count
title_short	Single phase asymmetrical multilevel inverter topology with reduced device count
title_full	Single phase asymmetrical multilevel inverter topology with reduced device count
title_fullStr	Single phase asymmetrical multilevel inverter topology with reduced device count
title_full_unstemmed	Single phase asymmetrical multilevel inverter topology with reduced device count
title_sort	single phase asymmetrical multilevel inverter topology with reduced device count
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2022
url	http://eprints.utm.my/id/eprint/101913/1/MSaadArifPSKE2022.pdf
_version_	1776100801747353600

Single phase asymmetrical multilevel inverter topology with reduced device count

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