Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture

Convolutional Neural Networks (CNNs) are hierarchical biologically-inspired models that may be taught to perform a variety of detection, identification, and segmentation tasks. The key processing requirements in the CNNs process are the multiplier-accumulator (MAC) operations in the convolution laye...

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Main Author:	Lee, Mei Xiang
Format:	Thesis
Language:	English
Published:	2022
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/102134/1/LeeMeiXiangMSKE2022.pdf.pdf
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id	my-utm-ep.102134
record_format	uketd_dc
spelling	my-utm-ep.1021342023-08-05T02:48:44Z Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture 2022 Lee, Mei Xiang TK Electrical engineering. Electronics Nuclear engineering Convolutional Neural Networks (CNNs) are hierarchical biologically-inspired models that may be taught to perform a variety of detection, identification, and segmentation tasks. The key processing requirements in the CNNs process are the multiplier-accumulator (MAC) operations in the convolution layer. A perfect fusion of various multipliers and adders would yield an ideal MAC for CNNs' convolution layer. Besides this, different kernel mask sizes are required throughout the convolution layer in CNNs, depending on demand. In general, each size of kernel mask requires a unique MAC architectural configuration, thus lengthening the time spent in research and development. To overcome this problem, a flexible MAC design has been developed that allows users to choose between different sizes depending on the requirements of the CNNs. This method, known as Selective Kernel Size, may activate kernel sizes from 1x1 to 7x7. This thesis also proposes a new MAC architecture called Mulitplier- Accumulator with Carry-Save-Adder (MACcsa ) to improve the MAC performance by efficiently computing the sum of three or more bits of input. Each proposed design is synthesized to Silterra 180 nm technology, and the time, power consumption, and cell area are all compared. Selective Kernel Size architecture demonstrates a substantial gain in terms of cell area and power from 56% to 80% when compared to mixing different sizes of MAC design in specific CNNs network, with some degradation in time delay. When comparing the classical addition structure to the proposed MAC with the CSA structure, results show that while the MAC with CSA is only slightly faster than the classical MAC, the power and cell area are improved by 4% to 10%. 2022 Thesis http://eprints.utm.my/id/eprint/102134/ http://eprints.utm.my/id/eprint/102134/1/LeeMeiXiangMSKE2022.pdf.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149249 masters Universiti Teknologi Malaysia Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Lee, Mei Xiang Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
description	Convolutional Neural Networks (CNNs) are hierarchical biologically-inspired models that may be taught to perform a variety of detection, identification, and segmentation tasks. The key processing requirements in the CNNs process are the multiplier-accumulator (MAC) operations in the convolution layer. A perfect fusion of various multipliers and adders would yield an ideal MAC for CNNs' convolution layer. Besides this, different kernel mask sizes are required throughout the convolution layer in CNNs, depending on demand. In general, each size of kernel mask requires a unique MAC architectural configuration, thus lengthening the time spent in research and development. To overcome this problem, a flexible MAC design has been developed that allows users to choose between different sizes depending on the requirements of the CNNs. This method, known as Selective Kernel Size, may activate kernel sizes from 1x1 to 7x7. This thesis also proposes a new MAC architecture called Mulitplier- Accumulator with Carry-Save-Adder (MACcsa ) to improve the MAC performance by efficiently computing the sum of three or more bits of input. Each proposed design is synthesized to Silterra 180 nm technology, and the time, power consumption, and cell area are all compared. Selective Kernel Size architecture demonstrates a substantial gain in terms of cell area and power from 56% to 80% when compared to mixing different sizes of MAC design in specific CNNs network, with some degradation in time delay. When comparing the classical addition structure to the proposed MAC with the CSA structure, results show that while the MAC with CSA is only slightly faster than the classical MAC, the power and cell area are improved by 4% to 10%.
format	Thesis
qualification_level	Master's degree
author	Lee, Mei Xiang
author_facet	Lee, Mei Xiang
author_sort	Lee, Mei Xiang
title	Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
title_short	Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
title_full	Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
title_fullStr	Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
title_full_unstemmed	Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
title_sort	integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture
granting_institution	Universiti Teknologi Malaysia
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2022
url	http://eprints.utm.my/id/eprint/102134/1/LeeMeiXiangMSKE2022.pdf.pdf
_version_	1776100853888843776

Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture

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