Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling

Designing integrated circuits (ICs) has become more challenging when fabrication technology scales down. Overheating has been acknowledged as a major issue in testing due to high power consumption of a chip during test. A direct consequence of the increasing power density is the increasing junction...

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Main Author:	Hassan, Hasliza
Format:	Thesis
Language:	English
Published:	2018
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/102249/1/HaslizaHassanPSKE2018.pdf
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spelling	my-utm-ep.1022492023-08-17T00:22:55Z Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling 2018 Hassan, Hasliza TK Electrical engineering. Electronics Nuclear engineering Designing integrated circuits (ICs) has become more challenging when fabrication technology scales down. Overheating has been acknowledged as a major issue in testing due to high power consumption of a chip during test. A direct consequence of the increasing power density is the increasing junction temperature that poses several problems such as aging issue. Therefore, thermal estimation needs to be considered during test scheduling to avoid exceeding temperature limit of the System-on-Chips under test. This thesis proposes a new thermal model that considers metal layer effects of SoC, and thermal safe test scheduling with dynamic voltage and frequency scaling (DVFS) technique. The difference in estimated temperature is over 10 °C if the effect of metal interconnect is neglected. In DVFS, the energy savings obtained by eliminating the global clock are, in many cases, offset by the additional power consumed due to longer execution time. The thermal safe test scheduling problem is formulated as a combination optimization problem, and the integer logic programming is used to find the optimal solution of test schedule for a given SoC under thermal constraint. The proposed thermal model is a necessary tool for rapid thermal analysis of the system which is exposed to non-uniform substrate temperature including thermal effect from metal interconnects. This thermal model will be used to estimate temperature during test scheduling in order to optimize total test time under thermal constraint. Results on different benchmark SoCs have shown the effectiveness of the proposed technique which produces shorter testing time. Total test time reduction by using the proposed technique is 46% compared to conventional existing techniques. Overall, the proposed technique produced more effective thermal aware test scheduling. 2018 Thesis http://eprints.utm.my/id/eprint/102249/ http://eprints.utm.my/id/eprint/102249/1/HaslizaHassanPSKE2018.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149000 phd doctoral Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Hassan, Hasliza Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
description	Designing integrated circuits (ICs) has become more challenging when fabrication technology scales down. Overheating has been acknowledged as a major issue in testing due to high power consumption of a chip during test. A direct consequence of the increasing power density is the increasing junction temperature that poses several problems such as aging issue. Therefore, thermal estimation needs to be considered during test scheduling to avoid exceeding temperature limit of the System-on-Chips under test. This thesis proposes a new thermal model that considers metal layer effects of SoC, and thermal safe test scheduling with dynamic voltage and frequency scaling (DVFS) technique. The difference in estimated temperature is over 10 °C if the effect of metal interconnect is neglected. In DVFS, the energy savings obtained by eliminating the global clock are, in many cases, offset by the additional power consumed due to longer execution time. The thermal safe test scheduling problem is formulated as a combination optimization problem, and the integer logic programming is used to find the optimal solution of test schedule for a given SoC under thermal constraint. The proposed thermal model is a necessary tool for rapid thermal analysis of the system which is exposed to non-uniform substrate temperature including thermal effect from metal interconnects. This thermal model will be used to estimate temperature during test scheduling in order to optimize total test time under thermal constraint. Results on different benchmark SoCs have shown the effectiveness of the proposed technique which produces shorter testing time. Total test time reduction by using the proposed technique is 46% compared to conventional existing techniques. Overall, the proposed technique produced more effective thermal aware test scheduling.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Hassan, Hasliza
author_facet	Hassan, Hasliza
author_sort	Hassan, Hasliza
title	Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
title_short	Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
title_full	Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
title_fullStr	Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
title_full_unstemmed	Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
title_sort	thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2018
url	http://eprints.utm.my/id/eprint/102249/1/HaslizaHassanPSKE2018.pdf
_version_	1776100878826078208

Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling

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