Register transfer level design of compression processor core using verilog hardware description language

Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types....

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Bibliographic Details
Main Author:	Mohd. Sabri, Roslee
Format:	Thesis
Language:	English
Published:	2007
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/11398/1/RosleeMohdSabriMFKE2007.pdf
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id	my-utm-ep.11398
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spelling	my-utm-ep.113982018-08-26T04:53:03Z Register transfer level design of compression processor core using verilog hardware description language 2007-11 Mohd. Sabri, Roslee TK Electrical engineering. Electronics Nuclear engineering Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types. However, several design limitations exist. The design uses several technology-dependent modules that limit its hardware realization in alternative technologies. In addition, it also suffers from an abnormal functional behavior when trying to decompress data that contain sufficiently high redundancy. In view of these limitations, design enhancements are proposed. One of the proposed enhancements is to improve the design portability to any hardware implementation technology. This is accomplished through designing generic hardware to replace the technology-dependent modules and utilizing conditional compilation approach to best decide the design realization given the available resources and constraints. With this approach, IP cores designed for the targeted technology should be used to take advantage of the efficient resource utilization and proven design, which leads to faster time-to-market and minimizes the integration risks and verification efforts of large systems. However, if the design does not have access to IP cores, then generic modules can be instantiated but at the expense of development cost. Another design enhancement offers a hardware patch to fix the decompression core hardware bug. The issue was identified to originate from writing and reading the same memory location simultaneously. As a solution, the behavior of the memory controller and its supporting logic are modified to prevent this from occurring. From the design simulation results, it is concluded that the decompression core hardware bug is finally solved. 2007-11 Thesis http://eprints.utm.my/id/eprint/11398/ http://eprints.utm.my/id/eprint/11398/1/RosleeMohdSabriMFKE2007.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mohd. Sabri, Roslee Register transfer level design of compression processor core using verilog hardware description language
description	Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types. However, several design limitations exist. The design uses several technology-dependent modules that limit its hardware realization in alternative technologies. In addition, it also suffers from an abnormal functional behavior when trying to decompress data that contain sufficiently high redundancy. In view of these limitations, design enhancements are proposed. One of the proposed enhancements is to improve the design portability to any hardware implementation technology. This is accomplished through designing generic hardware to replace the technology-dependent modules and utilizing conditional compilation approach to best decide the design realization given the available resources and constraints. With this approach, IP cores designed for the targeted technology should be used to take advantage of the efficient resource utilization and proven design, which leads to faster time-to-market and minimizes the integration risks and verification efforts of large systems. However, if the design does not have access to IP cores, then generic modules can be instantiated but at the expense of development cost. Another design enhancement offers a hardware patch to fix the decompression core hardware bug. The issue was identified to originate from writing and reading the same memory location simultaneously. As a solution, the behavior of the memory controller and its supporting logic are modified to prevent this from occurring. From the design simulation results, it is concluded that the decompression core hardware bug is finally solved.
format	Thesis
qualification_level	Master's degree
author	Mohd. Sabri, Roslee
author_facet	Mohd. Sabri, Roslee
author_sort	Mohd. Sabri, Roslee
title	Register transfer level design of compression processor core using verilog hardware description language
title_short	Register transfer level design of compression processor core using verilog hardware description language
title_full	Register transfer level design of compression processor core using verilog hardware description language
title_fullStr	Register transfer level design of compression processor core using verilog hardware description language
title_full_unstemmed	Register transfer level design of compression processor core using verilog hardware description language
title_sort	register transfer level design of compression processor core using verilog hardware description language
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2007
url	http://eprints.utm.my/id/eprint/11398/1/RosleeMohdSabriMFKE2007.pdf
_version_	1747814849295941632

Register transfer level design of compression processor core using verilog hardware description language

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