A hardware architecture of prewitt edge detection
The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge de...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | أطروحة |
| اللغة: | English |
| منشور في: |
2009
|
| الموضوعات: | |
| الوصول للمادة أونلاين: | http://eprints.utm.my/id/eprint/18328/1/ArameshSeifMFKE2009.pdf |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
| id |
my-utm-ep.18328 |
|---|---|
| record_format |
uketd_dc |
| spelling |
my-utm-ep.183282018-06-26T07:52:34Z A hardware architecture of prewitt edge detection 2009 Seif, Aramesh TK Electrical engineering. Electronics Nuclear engineering The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge detection system. The architecture is capable of operating with a clock frequency of 145 MHz at 550 frames per second. Computation error analysis performed shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab. 2009 Thesis http://eprints.utm.my/id/eprint/18328/ http://eprints.utm.my/id/eprint/18328/1/ArameshSeifMFKE2009.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering |
| institution |
Universiti Teknologi Malaysia |
| collection |
UTM Institutional Repository |
| language |
English |
| topic |
TK Electrical engineering Electronics Nuclear engineering |
| spellingShingle |
TK Electrical engineering Electronics Nuclear engineering Seif, Aramesh A hardware architecture of prewitt edge detection |
| description |
The objective of this project is to develop a real-time hardware architecture for Prewitt edge detection algorithm. Prewitt edge detection provides differencing operation in the single kernel. Verilog hardware description language was used as the hardware programming language for a real-time edge detection system. The architecture is capable of operating with a clock frequency of 145 MHz at 550 frames per second. Computation error analysis performed shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab. |
| format |
Thesis |
| qualification_level |
Master's degree |
| author |
Seif, Aramesh |
| author_facet |
Seif, Aramesh |
| author_sort |
Seif, Aramesh |
| title |
A hardware architecture of prewitt edge detection |
| title_short |
A hardware architecture of prewitt edge detection |
| title_full |
A hardware architecture of prewitt edge detection |
| title_fullStr |
A hardware architecture of prewitt edge detection |
| title_full_unstemmed |
A hardware architecture of prewitt edge detection |
| title_sort |
hardware architecture of prewitt edge detection |
| granting_institution |
Universiti Teknologi Malaysia, Faculty of Electrical Engineering |
| granting_department |
Faculty of Electrical Engineering |
| publishDate |
2009 |
| url |
http://eprints.utm.my/id/eprint/18328/1/ArameshSeifMFKE2009.pdf |
| _version_ |
1747815248148037632 |