A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter

Most of modern communication devices are implemented on portable systems powered by a battery with limited energy. Due to their dependence on batteries, some efforts have to be made to minimize the power consumption of these devices. One of the approaches is to use low power analog-to-digital conver...

Full description

Saved in:

Bibliographic Details
Main Author:	Yusoff, Yuzman
Format:	Thesis
Language:	English
Published:	2010
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/36566/5/YuzmanYusoffMFKE2010.pdf
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my-utm-ep.36566
record_format	uketd_dc
spelling	my-utm-ep.365662017-09-20T07:09:50Z A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter 2010-10 Yusoff, Yuzman TK Electrical engineering. Electronics Nuclear engineering TK7885-7895 Computer engineer. Computer hardware Most of modern communication devices are implemented on portable systems powered by a battery with limited energy. Due to their dependence on batteries, some efforts have to be made to minimize the power consumption of these devices. One of the approaches is to use low power analog-to-digital converter (ADC). This thesis focuses on the design implementation of low power pipelined ADC for wireless communication system. The pipelined ADC was realized using 1.5-bit per-stage structures with digital error correction. For power reduction, dedicated front-end sample-and-hold circuit used in conventional pipelined ADC architecture is removed. Furthermore, power analysis has been performed using MATLAB® to assist in determining the best stage resolution in pipelined stages. A dynamic comparator is employed to optimize further the power consumption in pipelined stages. This low power pipelined ADC is implemented using Siltera’s 0.18µm, 1.8-3.3V complementary metal oxide semiconductor process, with double layer poly-silicon and five metal layers. The designed pipelined ADC exhibits a 10-bit resolution at 50 Mega-Sample per-second and 50.82dB signal to noise and distortion ratio with an effective number of bits of 8.15-bit. The differential non-linearity (DNL) and the integral non-linearity (INL) are ±1 least-significant of bits (LSB). The power consumption is 97mW from a 3V supply and the entire area of the pipelined ADC including input and output pads is 2.4mm2. 2010-10 Thesis http://eprints.utm.my/id/eprint/36566/ http://eprints.utm.my/id/eprint/36566/5/YuzmanYusoffMFKE2010.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering TK Electrical engineering Electronics Nuclear engineering Yusoff, Yuzman A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
description	Most of modern communication devices are implemented on portable systems powered by a battery with limited energy. Due to their dependence on batteries, some efforts have to be made to minimize the power consumption of these devices. One of the approaches is to use low power analog-to-digital converter (ADC). This thesis focuses on the design implementation of low power pipelined ADC for wireless communication system. The pipelined ADC was realized using 1.5-bit per-stage structures with digital error correction. For power reduction, dedicated front-end sample-and-hold circuit used in conventional pipelined ADC architecture is removed. Furthermore, power analysis has been performed using MATLAB® to assist in determining the best stage resolution in pipelined stages. A dynamic comparator is employed to optimize further the power consumption in pipelined stages. This low power pipelined ADC is implemented using Siltera’s 0.18µm, 1.8-3.3V complementary metal oxide semiconductor process, with double layer poly-silicon and five metal layers. The designed pipelined ADC exhibits a 10-bit resolution at 50 Mega-Sample per-second and 50.82dB signal to noise and distortion ratio with an effective number of bits of 8.15-bit. The differential non-linearity (DNL) and the integral non-linearity (INL) are ±1 least-significant of bits (LSB). The power consumption is 97mW from a 3V supply and the entire area of the pipelined ADC including input and output pads is 2.4mm2.
format	Thesis
qualification_level	Master's degree
author	Yusoff, Yuzman
author_facet	Yusoff, Yuzman
author_sort	Yusoff, Yuzman
title	A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
title_short	A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
title_full	A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
title_fullStr	A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
title_full_unstemmed	A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
title_sort	10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2010
url	http://eprints.utm.my/id/eprint/36566/5/YuzmanYusoffMFKE2010.pdf
_version_	1747816435552354304

A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter

Similar Items