FPGA implementation a reconfigurable address generation unit for image processing applications

Nowadays, the DSP algorithms are being widely used in the world of digital image processing. Example of the DSP algorithms that used in image processing is 2D correlation, 2D convolution, fast Fourier transforms, FIR filter and etc. The performance of the DSP algorithm is highly depends on its proce...

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Bibliographic Details
Main Author:	Kok Horng, Kok Horng
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/36803/5/KamKokHorngMFKE2013.pdf
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id	my-utm-ep.36803
record_format	uketd_dc
spelling	my-utm-ep.368032017-07-16T05:55:58Z FPGA implementation a reconfigurable address generation unit for image processing applications 2013-06 Kok Horng, Kok Horng TK Electrical engineering. Electronics Nuclear engineering Nowadays, the DSP algorithms are being widely used in the world of digital image processing. Example of the DSP algorithms that used in image processing is 2D correlation, 2D convolution, fast Fourier transforms, FIR filter and etc. The performance of the DSP algorithm is highly depends on its processing speed and memory bandwidth. Those algorithms require intensive data manipulation and calculation happens in parallel. The DSP algorithms also require complex address pattern calculation. The DSP processor needs to handle the data processing and also complex address calculation in the same time. The complex address pattern calculation using RISC processor is not efficient and therefore slower down the overall memory access speed. Hence, a dedicated hardware blocks to perform the address generation is essential. Such hardware known as Address Generation Unit(AGU). The prior arts of AGU have limitations as some of the AGU do not able to handle image edge condition and data reuse. Besides that, the prior art of the AGU have not been verified in the actual SOC environment. In this project, a reconfigurable AGU that targeted for 2D correlation, sum of absolute difference and Finite Impulse Response (FIR) is proposed. The proposed AGU able to take care of the image edge conditions by padding it with edge pixels. The proposed AGU also being integrated into the Altera Avalon fabric and fully verified in Altera DE2-70 FPGA. It also shows 30% to 40% improvements in the performance at certain area. 2013-06 Thesis http://eprints.utm.my/id/eprint/36803/ http://eprints.utm.my/id/eprint/36803/5/KamKokHorngMFKE2013.pdf application/pdf en public masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Kok Horng, Kok Horng FPGA implementation a reconfigurable address generation unit for image processing applications
description	Nowadays, the DSP algorithms are being widely used in the world of digital image processing. Example of the DSP algorithms that used in image processing is 2D correlation, 2D convolution, fast Fourier transforms, FIR filter and etc. The performance of the DSP algorithm is highly depends on its processing speed and memory bandwidth. Those algorithms require intensive data manipulation and calculation happens in parallel. The DSP algorithms also require complex address pattern calculation. The DSP processor needs to handle the data processing and also complex address calculation in the same time. The complex address pattern calculation using RISC processor is not efficient and therefore slower down the overall memory access speed. Hence, a dedicated hardware blocks to perform the address generation is essential. Such hardware known as Address Generation Unit(AGU). The prior arts of AGU have limitations as some of the AGU do not able to handle image edge condition and data reuse. Besides that, the prior art of the AGU have not been verified in the actual SOC environment. In this project, a reconfigurable AGU that targeted for 2D correlation, sum of absolute difference and Finite Impulse Response (FIR) is proposed. The proposed AGU able to take care of the image edge conditions by padding it with edge pixels. The proposed AGU also being integrated into the Altera Avalon fabric and fully verified in Altera DE2-70 FPGA. It also shows 30% to 40% improvements in the performance at certain area.
format	Thesis
qualification_level	Master's degree
author	Kok Horng, Kok Horng
author_facet	Kok Horng, Kok Horng
author_sort	Kok Horng, Kok Horng
title	FPGA implementation a reconfigurable address generation unit for image processing applications
title_short	FPGA implementation a reconfigurable address generation unit for image processing applications
title_full	FPGA implementation a reconfigurable address generation unit for image processing applications
title_fullStr	FPGA implementation a reconfigurable address generation unit for image processing applications
title_full_unstemmed	FPGA implementation a reconfigurable address generation unit for image processing applications
title_sort	fpga implementation a reconfigurable address generation unit for image processing applications
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2013
url	http://eprints.utm.my/id/eprint/36803/5/KamKokHorngMFKE2013.pdf
_version_	1747816460948865024

FPGA implementation a reconfigurable address generation unit for image processing applications

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