Hardware acceleration of 2D convolution using systolic array

Two-dimensional convolution is a prevalent mathematical operation used in different areas of digital signal processing such as image processing, video processing and analog signal transmission. The computation intensive nature of 2D convolution operation along with the stringent demand of real-time...

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Main Author:	Wong, Xue Yuan
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/53576/1/WongXueYuanmfke2015.pdf
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id	my-utm-ep.53576
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spelling	my-utm-ep.535762020-07-21T08:08:28Z Hardware acceleration of 2D convolution using systolic array 2015-06 Wong, Xue Yuan TK Electrical engineering. Electronics Nuclear engineering Two-dimensional convolution is a prevalent mathematical operation used in different areas of digital signal processing such as image processing, video processing and analog signal transmission. The computation intensive nature of 2D convolution operation along with the stringent demand of real-time image processing in term of response time and throughput rate dismiss the viability of general-purpose processor to be used as part of the image processing solutions. Thus, the design work of a fully-dedicated 2D convolution hardware based on systolic array architecture with integrated pipeline design is proposed in this project in order to achieve optimum hardware performance in term of processing time and throughput rate. To achieve the objective, the entire hardware design is fully described in SystemVerilog and cut-set systolization procedure is applied to map 2D convolution algorithm to a 3 x 3 based systolic array hardware design. Upon the end of design and integration, the accelerated 2D convolution hardware design goes through performance benchmark. Based on the performance benchmark report, the implemented 2D convolution hardware is capable to achieve a throughput rate of 168M outputs per second. In addition, it takes 1.54 ms to complete the execution of 2D convolution based on 512 x 512 grayscale image. In comparison with general-purpose processor, the implemented design outperforms general-purpose processor in term of execution speed by 43%. The performance breakthrough marks an important milestone to the pipelined 2D convolution hardware design based on systolic array architecture as the design is proven to be essential for the future use of real-time image processing. 2015-06 Thesis http://eprints.utm.my/id/eprint/53576/ http://eprints.utm.my/id/eprint/53576/1/WongXueYuanmfke2015.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:85663 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Wong, Xue Yuan Hardware acceleration of 2D convolution using systolic array
description	Two-dimensional convolution is a prevalent mathematical operation used in different areas of digital signal processing such as image processing, video processing and analog signal transmission. The computation intensive nature of 2D convolution operation along with the stringent demand of real-time image processing in term of response time and throughput rate dismiss the viability of general-purpose processor to be used as part of the image processing solutions. Thus, the design work of a fully-dedicated 2D convolution hardware based on systolic array architecture with integrated pipeline design is proposed in this project in order to achieve optimum hardware performance in term of processing time and throughput rate. To achieve the objective, the entire hardware design is fully described in SystemVerilog and cut-set systolization procedure is applied to map 2D convolution algorithm to a 3 x 3 based systolic array hardware design. Upon the end of design and integration, the accelerated 2D convolution hardware design goes through performance benchmark. Based on the performance benchmark report, the implemented 2D convolution hardware is capable to achieve a throughput rate of 168M outputs per second. In addition, it takes 1.54 ms to complete the execution of 2D convolution based on 512 x 512 grayscale image. In comparison with general-purpose processor, the implemented design outperforms general-purpose processor in term of execution speed by 43%. The performance breakthrough marks an important milestone to the pipelined 2D convolution hardware design based on systolic array architecture as the design is proven to be essential for the future use of real-time image processing.
format	Thesis
qualification_level	Master's degree
author	Wong, Xue Yuan
author_facet	Wong, Xue Yuan
author_sort	Wong, Xue Yuan
title	Hardware acceleration of 2D convolution using systolic array
title_short	Hardware acceleration of 2D convolution using systolic array
title_full	Hardware acceleration of 2D convolution using systolic array
title_fullStr	Hardware acceleration of 2D convolution using systolic array
title_full_unstemmed	Hardware acceleration of 2D convolution using systolic array
title_sort	hardware acceleration of 2d convolution using systolic array
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2015
url	http://eprints.utm.my/id/eprint/53576/1/WongXueYuanmfke2015.pdf
_version_	1747817585695522816

Hardware acceleration of 2D convolution using systolic array

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