Hardware acceleration of 2D convolution using systolic array

Hardware acceleration of 2D convolution using systolic array

Two-dimensional convolution is a prevalent mathematical operation used in different areas of digital signal processing such as image processing, video processing and analog signal transmission. The computation intensive nature of 2D convolution operation along with the stringent demand of real-time...

Saved in:

書目詳細資料
主要作者:	Wong, Xue Yuan
格式:	Thesis
語言:	English
出版:	2015
主題:	TK Electrical engineering Electronics Nuclear engineering
在線閱讀:	http://eprints.utm.my/id/eprint/53576/1/WongXueYuanmfke2015.pdf
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

相似書籍

Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
由: Mohammed, Mohammed Isam Eldin Hassan
出版: (2020)

An embedded system for networking security applying cryptographic acceleration in field programmable gate array hardware
由: Paramasivam, Vishnu
出版: (2009)

Systolic array architecture and its application in finite impulse response filter design
由: Kadir, Ezdiani Idayu
出版: (2013)

Principal component analysis hardware acceleration
由: Ng, Yee Wei
出版: (2020)

Convolution and max pooling layer accelerator for convolutional neural network
由: Goh, Jinn Chyn
出版: (2020)

Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays
由: Liew, Tek Yee
出版: (2011)

Hardware acceleration of secure hash algorithm 3
由: Ng, Lai Boon
出版: (2020)

Hardware accelerator implementation of colour correction algorithm
由: Loh, Shu Ting
出版: (2020)

Hardware based accelerator for database query using M-tree
由: Chai, Kah Hieng
出版: (2018)

Electrocardiogram QRS detection hardware accelerator for ASIC implementation
由: Lim, Zhi Qing
出版: (2020)

Support vector machine hardware accelerator for tongue colour diagnosis
由: Thiah, Amanda Su Lin
出版: (2020)

Face detection hardware accelerator using C-based high-level synthesis
由: Yeap, Han Chien
出版: (2018)

8192 bit Rivest-Shamir-Adleman data encryption hardware accelerator
由: Chew, Yen Wen
出版: (2015)

1-D and 2-D convolution neural network for bird sound detection
由: Tee, Yun Hong
出版: (2020)

FPGA implementation of Image processing 2D convolution for spatial filter
由: Ng, Bee Yee
出版: (2012)

Hardware-based genetic algorithm implementation in field programmable gate arrays
由: Balakrishnan, Sathivellu
出版: (2012)

Comparison of 1D VS 2D convolutional neural networks for bird sound detection
由: Tan, Pei Hong
出版: (2022)

Hardware Implementation Of 2-D Discrete Wavelet Transform For JPEG 2000 Using Lifting Scheme
由: Bhuyan, Mohammad Shaharia
出版: (2008)

Hardware implementation of coordinate rotation digital computer in field programmable gate array
由: Mohd. Sazali, Mohd. Ilyas Sobirin
出版: (2012)

Stochastic computing system hardware design for convolutional neural networks optimized for accuracy area and energy efficiency
由: Hamdan, Hamdan Usamah
出版: (2020)

2D convolutional neural network for the detection of Asian Koel (Eudynamys Scolopaceus) vocalizations
由: Musa, Nurfaizah
出版: (2020)

Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing
由: Ch'ng, Heng Sun
出版: (2007)

Configurable version management hardware transactional memory for embedded multiprocessor field-programmable gate array
由: Sirkunan, Jeevan
出版: (2015)

An embedded cryptosystem implementing symmetric cipher and public-key crypto algorithms in hardware
由: Hau, Yuan Wen
出版: (2005)

Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
由: Ooi, Tze Kian
出版: (2022)

Hardware implementation using FPGA for barcode reader
由: Marzuki, Ade Syaheda Wani
出版: (2008)

Video annotation using convolution neural network
由: Wan Abd. Kadir, Wan Zahiruddin
出版: (2018)

Implementation of instruction decoding logic using hardware and software
由: Su, Chee Siong
出版: (2010)

Magnetohydrodynamic accelerator with equilibrium plasma
由: Sukarsan, Sukarsan
出版: (2010)

Magnetohydrodynamic accelerator with equilibrium plasma
由: Sukarsan, Sukarsan
出版: (2009)

Hardware core of pipelined thinning algorithm
由: Noordin, Mohamad Amin
出版: (2015)

Implementation of reconfigurable viterbi decoders in hardware
由: Noor Batcha, Mohamed Farid
出版: (2010)

Antenna array at 2.4 GHZ for point to point communication
由: Moftah Almahroug, AlHasan Ali
出版: (2007)

Antenna array at 2.4 GHZ using circular polarization for point to point communication
由: F. Esseid, Ali Guima
出版: (2007)

Bird species identification using spectrograms and convolutional neural networks
由: Saad, Aymen
出版: (2020)

Tongue colour diagnosis system using convolutional neural network
由: Tan, Yi Chen
出版: (2020)

The use of convolutional coding to reduce bit error rate in CDMA
由: Mohamad Noor, Norhayati
出版: (2001)

A hardware architecture of prewitt edge detection
由: Seif, Aramesh
出版: (2009)

Single board computer based hardware-input
由: A. Hassan, Walid
出版: (2009)

Power efficient blockchain miner accelerator design
由: Lim, Calvin
出版: (2022)

Services hosted by the Perpustakaan Sultan Abdul Samad, Universiti Putra Malaysia with Cooperation MySyL Group