Hardware acceleration of 2D convolution using systolic array

相似书籍

• Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
  由: Mohammed, Mohammed Isam Eldin Hassan
  出版: (2020)
• An embedded system for networking security applying cryptographic acceleration in field programmable gate array hardware
  由: Paramasivam, Vishnu
  出版: (2009)
• Systolic array architecture and its application in finite impulse response filter design
  由: Kadir, Ezdiani Idayu
  出版: (2013)
• Principal component analysis hardware acceleration
  由: Ng, Yee Wei
  出版: (2020)
• Convolution and max pooling layer accelerator for convolutional neural network
  由: Goh, Jinn Chyn
  出版: (2020)