Verilog design of input/output processor with built-in-self-test

This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. Th...

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Goh, Keng Hoo
التنسيق:	أطروحة
اللغة:	English
منشور في:	2007
الموضوعات:	TK Electrical engineering Electronics Nuclear engineering
الوصول للمادة أونلاين:	http://eprints.utm.my/id/eprint/5959/1/GohKengHooMFKE2007.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

id	my-utm-ep.5959
record_format	uketd_dc
spelling	my-utm-ep.59592018-09-27T04:01:29Z Verilog design of input/output processor with built-in-self-test 2007-04 Goh, Keng Hoo TK Electrical engineering. Electronics Nuclear engineering This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. The embedded BIST capability in IOP designed in this project has the objectives to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to IOP while Multiple Input Signature Register (MISR) is able to compact the IOP output response into a manageable signature size. In this project, the designed is coded in Verilog hardware description language at register transfer level (RTL), synthesized using Altera Quartus II using FPFA device from APEC20KE family, RTL level compilation and simulation using Modelsim v6.1b and gate level timing simulation using Modelsim-Altera v6.1g. This project was scheduled for two semester in which the activities to study and determine hardware specifications, requirements, functionalities and Verilog HDL migration were done in first semester whereas activities to design, synthesis, compile, simulate, and validate were carried out in semester 2. IOP with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained and the ability of the BIST block provides high fault coverage. 2007-04 Thesis http://eprints.utm.my/id/eprint/5959/ http://eprints.utm.my/id/eprint/5959/1/GohKengHooMFKE2007.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:62149 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Goh, Keng Hoo Verilog design of input/output processor with built-in-self-test
description	This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. The embedded BIST capability in IOP designed in this project has the objectives to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to IOP while Multiple Input Signature Register (MISR) is able to compact the IOP output response into a manageable signature size. In this project, the designed is coded in Verilog hardware description language at register transfer level (RTL), synthesized using Altera Quartus II using FPFA device from APEC20KE family, RTL level compilation and simulation using Modelsim v6.1b and gate level timing simulation using Modelsim-Altera v6.1g. This project was scheduled for two semester in which the activities to study and determine hardware specifications, requirements, functionalities and Verilog HDL migration were done in first semester whereas activities to design, synthesis, compile, simulate, and validate were carried out in semester 2. IOP with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained and the ability of the BIST block provides high fault coverage.
format	Thesis
qualification_level	Master's degree
author	Goh, Keng Hoo
author_facet	Goh, Keng Hoo
author_sort	Goh, Keng Hoo
title	Verilog design of input/output processor with built-in-self-test
title_short	Verilog design of input/output processor with built-in-self-test
title_full	Verilog design of input/output processor with built-in-self-test
title_fullStr	Verilog design of input/output processor with built-in-self-test
title_full_unstemmed	Verilog design of input/output processor with built-in-self-test
title_sort	verilog design of input/output processor with built-in-self-test
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2007
url	http://eprints.utm.my/id/eprint/5959/1/GohKengHooMFKE2007.pdf
_version_	1747814616888508416

Verilog design of input/output processor with built-in-self-test

مواد مشابهة