Time and frequency characterization of the high speed I/O data bus
High speed data transfer between the CPU and peripherals on the PC motherboard is needed to support data traffic in future generation applications such as multimedia, games and broadband networks. The High Speed I/O data bus is developed to meet these applications. At high speed with multi Gbits/sec...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2007
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/5965/1/JimmyHuangHuatSinceMFKE2007.pdf |
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| Summary: | High speed data transfer between the CPU and peripherals on the PC motherboard is needed to support data traffic in future generation applications such as multimedia, games and broadband networks. The High Speed I/O data bus is developed to meet these applications. At high speed with multi Gbits/sec, impedance mismatch between the CPU and peripherals becomes critical and limits the possible maximum throughput. This effect can be modeled as a convolution process where the I/O bus behaves as a linear time invariant system that is defined by a channel impulse and frequency response. Since there are variations in the characteristic of the motherboards due to the fabrication and assembly process, it is desired to estimate the impulse response and frequency response of the High Speed I/O bus. This information can be used to gage the capability of the motherboard and use it as feedback to the relevant fabrication and assembly processes. By using simulation on MATLAB and EDA tools, two candidate methods will be evaluated: Impulse response and correlation method using simulated channel characteristics. Robustness of both methods will be evaluated in the presence of noise and cross talk. Further evaluation will be performed on data collected from actual production test of the I/O Bus. This is to evaluate the capability of the evaluated methods under actual manufacturing environment. |
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