Arithmetic logic unit design for silicon nanowire field-effect transistors logic

As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gat...

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Main Author:	Mohd. Munir Zahari, Nor Hafizah
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/78312/1/NorHafizahMohdMunirZahariMFKE20151.pdf
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spelling	my-utm-ep.783122018-08-20T07:25:29Z Arithmetic logic unit design for silicon nanowire field-effect transistors logic 2015-01 Mohd. Munir Zahari, Nor Hafizah TK Electrical engineering. Electronics Nuclear engineering As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gate and FinFET has been studied as potential structure to replace MOSFET. Thus this research report will describes the simulation and characterization of surrounded gate Silicon Nanowires Transistor (Si NWT). The cylindrical Gate-all around (GAA) Si NWT has showed robustness against SCE, ideal sub threshold swing, suppresses corner effect and suitable for low power devices. From this study simulation had proven that GAA Si NWT provides the best short channel device performance. Also highlighted in this research studies, to achieve symmetrical current in PMOS and NMOS, different number of nanowires channel is selected. Therefore by choosing large number of nanowires channel for PMOS transistor can help compensated the low value of hole mobility. In this work, 2:3 ratios of NMOS and PMOS channel of inverter had used as benchmark for ALU designed. Using the circuit modeling HSPICE, performance for Arithmetic Logic Unit (ALU) circuit in 30nm technology is analyzed with Silicon Nanowire (Si NW) compared with conventional planar MOSFET. The assessment of this circuit logic performance metric includes propagation delay, power-delay-product (PDP) and energy-delay-product (EDP) of full adder, XOR, AND and OR gate forming the ALU block. Moreover, ALU is built with less transistor count to implement Boolean expressions which help to reduced average power consumption, and delay. 2015-01 Thesis http://eprints.utm.my/id/eprint/78312/ http://eprints.utm.my/id/eprint/78312/1/NorHafizahMohdMunirZahariMFKE20151.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:80583 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Mohd. Munir Zahari, Nor Hafizah Arithmetic logic unit design for silicon nanowire field-effect transistors logic
description	As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gate and FinFET has been studied as potential structure to replace MOSFET. Thus this research report will describes the simulation and characterization of surrounded gate Silicon Nanowires Transistor (Si NWT). The cylindrical Gate-all around (GAA) Si NWT has showed robustness against SCE, ideal sub threshold swing, suppresses corner effect and suitable for low power devices. From this study simulation had proven that GAA Si NWT provides the best short channel device performance. Also highlighted in this research studies, to achieve symmetrical current in PMOS and NMOS, different number of nanowires channel is selected. Therefore by choosing large number of nanowires channel for PMOS transistor can help compensated the low value of hole mobility. In this work, 2:3 ratios of NMOS and PMOS channel of inverter had used as benchmark for ALU designed. Using the circuit modeling HSPICE, performance for Arithmetic Logic Unit (ALU) circuit in 30nm technology is analyzed with Silicon Nanowire (Si NW) compared with conventional planar MOSFET. The assessment of this circuit logic performance metric includes propagation delay, power-delay-product (PDP) and energy-delay-product (EDP) of full adder, XOR, AND and OR gate forming the ALU block. Moreover, ALU is built with less transistor count to implement Boolean expressions which help to reduced average power consumption, and delay.
format	Thesis
qualification_level	Master's degree
author	Mohd. Munir Zahari, Nor Hafizah
author_facet	Mohd. Munir Zahari, Nor Hafizah
author_sort	Mohd. Munir Zahari, Nor Hafizah
title	Arithmetic logic unit design for silicon nanowire field-effect transistors logic
title_short	Arithmetic logic unit design for silicon nanowire field-effect transistors logic
title_full	Arithmetic logic unit design for silicon nanowire field-effect transistors logic
title_fullStr	Arithmetic logic unit design for silicon nanowire field-effect transistors logic
title_full_unstemmed	Arithmetic logic unit design for silicon nanowire field-effect transistors logic
title_sort	arithmetic logic unit design for silicon nanowire field-effect transistors logic
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2015
url	http://eprints.utm.my/id/eprint/78312/1/NorHafizahMohdMunirZahariMFKE20151.pdf
_version_	1747817958490505216

Arithmetic logic unit design for silicon nanowire field-effect transistors logic

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