Arithmetic logic unit design for silicon nanowire field-effect transistors logic
As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gat...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Thesis |
| 語言: | English |
| 出版: |
2015
|
| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/78312/1/NorHafizahMohdMunirZahariMFKE20151.pdf |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|