Arithmetic logic unit design for silicon nanowire field-effect transistors logic
As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gat...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/78312/1/NorHafizahMohdMunirZahariMFKE20151.pdf |
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