The design of an FPGA-based sinusoidal pulse width modulation generator

The output of a DC to AC converter circuit is not a pure sine wave. To overcome this problem, a technique called sinusoidal pulse width modulation (SPWM) is used. Generation of SPWM requires a carrier wave and a reference wave. The reference wave is typically a sine wave. Many algorithms have been p...

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Main Author:	Yunos, Mohamed Shaharudeen
Format:	Thesis
Language:	English
Published:	2014
Subjects:	QA75 Electronic computers Computer science
Online Access:	http://eprints.utm.my/id/eprint/78754/1/MohamedShaharudeenYunosMAIS2014.pdf
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spelling	my-utm-ep.787542018-08-30T08:07:46Z The design of an FPGA-based sinusoidal pulse width modulation generator 2014-06 Yunos, Mohamed Shaharudeen QA75 Electronic computers. Computer science The output of a DC to AC converter circuit is not a pure sine wave. To overcome this problem, a technique called sinusoidal pulse width modulation (SPWM) is used. Generation of SPWM requires a carrier wave and a reference wave. The reference wave is typically a sine wave. Many algorithms have been proposed in the past to optimize the generation of the sine wave but the most suitable scheme uses a lookup table (LUT). In this project the SPWM is implemented using a field programmable gate array (FPGA) where discrete sine values are stored as lookup table in the FPGA. The challenge here is developing an algorithm to minimize the size of the LUT specifically and the FPGA, as a whole. Three SPWM designs are proposed in the project using the VHDL hardware descriptive language. Simulations are done using Mentor Graphic’s ModelSim SE 6.4 and the synthesis tool is Altera’s Quartus II Web Edition version 9.1. The proposed designs use two approaches, namely, the symmetrical properties of the sine wave to reduce the LUT size and also improvements in the programming codes to reduce the use of logic elements. Each of the proposed synthesized designs uses less than 40% of logic elements compared to the designs from previous works. 2014-06 Thesis http://eprints.utm.my/id/eprint/78754/ http://eprints.utm.my/id/eprint/78754/1/MohamedShaharudeenYunosMAIS2014.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:105908 masters Universiti Teknologi Malaysia, Advanced Informatics School Advanced Informatics School
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	QA75 Electronic computers Computer science
spellingShingle	QA75 Electronic computers Computer science Yunos, Mohamed Shaharudeen The design of an FPGA-based sinusoidal pulse width modulation generator
description	The output of a DC to AC converter circuit is not a pure sine wave. To overcome this problem, a technique called sinusoidal pulse width modulation (SPWM) is used. Generation of SPWM requires a carrier wave and a reference wave. The reference wave is typically a sine wave. Many algorithms have been proposed in the past to optimize the generation of the sine wave but the most suitable scheme uses a lookup table (LUT). In this project the SPWM is implemented using a field programmable gate array (FPGA) where discrete sine values are stored as lookup table in the FPGA. The challenge here is developing an algorithm to minimize the size of the LUT specifically and the FPGA, as a whole. Three SPWM designs are proposed in the project using the VHDL hardware descriptive language. Simulations are done using Mentor Graphic’s ModelSim SE 6.4 and the synthesis tool is Altera’s Quartus II Web Edition version 9.1. The proposed designs use two approaches, namely, the symmetrical properties of the sine wave to reduce the LUT size and also improvements in the programming codes to reduce the use of logic elements. Each of the proposed synthesized designs uses less than 40% of logic elements compared to the designs from previous works.
format	Thesis
qualification_level	Master's degree
author	Yunos, Mohamed Shaharudeen
author_facet	Yunos, Mohamed Shaharudeen
author_sort	Yunos, Mohamed Shaharudeen
title	The design of an FPGA-based sinusoidal pulse width modulation generator
title_short	The design of an FPGA-based sinusoidal pulse width modulation generator
title_full	The design of an FPGA-based sinusoidal pulse width modulation generator
title_fullStr	The design of an FPGA-based sinusoidal pulse width modulation generator
title_full_unstemmed	The design of an FPGA-based sinusoidal pulse width modulation generator
title_sort	design of an fpga-based sinusoidal pulse width modulation generator
granting_institution	Universiti Teknologi Malaysia, Advanced Informatics School
granting_department	Advanced Informatics School
publishDate	2014
url	http://eprints.utm.my/id/eprint/78754/1/MohamedShaharudeenYunosMAIS2014.pdf
_version_	1747818063123709952

The design of an FPGA-based sinusoidal pulse width modulation generator

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