Performance analysis of 22NM FinFET-based 8T SRAM cell
As CMOS devices are approaching nanometer regime, there are a lot of consequences found in scaling down CMOS devices such as short channel effects and process variations which affect the reliability and performance of the devices. Researchers have found that FinFET is one of the outstanding nominee...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/78938/1/NurHasnifaHasanMFKE2018.pdf |
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| Summary: | As CMOS devices are approaching nanometer regime, there are a lot of consequences found in scaling down CMOS devices such as short channel effects and process variations which affect the reliability and performance of the devices. Researchers have found that FinFET is one of the outstanding nominee to overcome this issue since FinFET has better control over the channel and the lower overall capacitance which will increase the performance of the 6T Static Random Access Memory (SRAM) circuit design. It will help in reducing bitline loading and hence improve SRAM performance. The conventional 6T SRAM cell suffers serious stability degradation issue due to access disturbance at low power mode. The major problem in 6T SRAM is that, when the output voltage reduced below the threshold voltage of the transistor, it will destroy the read operation of the 6T SRAM cell. The noises are easy to destruct the stored-data in the nodes of the 6T SRAM cell due to the direct path between storage nodes and bit lines. To overcome this issue, an 8T SRAM cell has been proposed where the read stability is expected to improve. The purpose of this study is to simulate and evaluate the performance of FinFET-based 6T SRAM and 8T SRAM cell and compare their results. In 8T SRAM, the two additional access transistors eliminate the discharging path from RBL to ground in 6T SRAM cell which in turn help in improving the stability of read operation in 8T SRAM. The stability of SRAM cell is determined by the butterfly curve which is obtained by combining the voltage transfer curve (VTC) of the two cross-coupled inverters of the SRAM cell. GTS Framework TCAD tool is used to design and simulate the FinFET device structure, the schematic and the layout of SRAM cell. From the findings, the FinFET gives better Vth, DIBL, SS and ION than MOSFET. In addition, 6T and 8T FinFET-based SRAM cell have shown a better stability than 6T and 8T MOSFET-based SRAM cell in retention mode, read mode and write mode. Compared to FinFET-based 6T SRAM cell, FinFET-based 8T SRAM cell improved the read stability by 68.5% and not causing any degradation on the write and retention noise margin. |
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