Optimization of n-channel silicon nanowire field effect transistor using Taguchi method

In the last few decades, the performance of electronics devices, especially the transistors have made tremendous progress thanks to the novel metal-oxidesemiconductor field-effect-transistor (MOSFET) devices structure like Silicon Nanowire FET (SNWFET). As the device is scaled down into nanometer re...

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Main Author:	Wahab, Nurul Eryana
Format:	Thesis
Language:	English
Published:	2018
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/78957/1/NurulEryanaWahabMFKE2018.pdf
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spelling	my-utm-ep.789572018-09-19T05:13:04Z Optimization of n-channel silicon nanowire field effect transistor using Taguchi method 2018-01 Wahab, Nurul Eryana TK Electrical engineering. Electronics Nuclear engineering In the last few decades, the performance of electronics devices, especially the transistors have made tremendous progress thanks to the novel metal-oxidesemiconductor field-effect-transistor (MOSFET) devices structure like Silicon Nanowire FET (SNWFET). As the device is scaled down into nanometer regime, SNWFET is believed could overcome the short channel effects (SCEs). The complexity of SNWFET is influenced by its device geometry such as gate and width size, nanowire shape, nanowire radius, channel orientation, etc. Therefore, the thesis describes the optimization of n-channel SNWFET by using Taguchi method. Taguchi method is straightforward, easy to apply and has fast simulation run time. The dimension of the SNWFET device i.e. gate length (Lg ) , silicon nanowire radius (Rnw) and gate oxide thickness (Tax) are altered for a range of sizes and dimensions by using Taguchi approach to get the most optimum dimensions of the device. The electrical properties of the SNWFET device which are threshold voltage (Vth), on/off current ratio (Ion/Iott ratio), Subthreshold Swing (55), and Drain-Induced Barrier Lowering (DIBL) are extracted and analyzed based on the I-V characteristics. The general idea of the Taguchi technique is the set of electrical properties are statistically distributed into standard normal distribution and the mean and the standard deviation are determined. From the results obtained, with fixed thin Tax, as the Rnw is reduces and Lg is increases, the electrical performance of the SNWFET device is better in terms of its subthreshold swing, switching speed and DIBL. Better threshold is observed in nSNWFET device with smaller Rnw. The Ion/Iott ratio also shows better result with longer Lg . Lastly, from the statistical analytic of the device's electrical characteristics, the most optimum device dimensions of n-channel SNWFET device structure has been successfully identified which are Rnw at 3nm, Tax at 3nm, and Lg at 40nm with their electrical characteristics of Vt h , Ion/Iott ratio, 55 and DIBL are O.22V, I.06xI05 , 64.69mVIdee and = 80.27mV/V respectively. 2018-01 Thesis http://eprints.utm.my/id/eprint/78957/ http://eprints.utm.my/id/eprint/78957/1/NurulEryanaWahabMFKE2018.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:108539 masters Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Wahab, Nurul Eryana Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
description	In the last few decades, the performance of electronics devices, especially the transistors have made tremendous progress thanks to the novel metal-oxidesemiconductor field-effect-transistor (MOSFET) devices structure like Silicon Nanowire FET (SNWFET). As the device is scaled down into nanometer regime, SNWFET is believed could overcome the short channel effects (SCEs). The complexity of SNWFET is influenced by its device geometry such as gate and width size, nanowire shape, nanowire radius, channel orientation, etc. Therefore, the thesis describes the optimization of n-channel SNWFET by using Taguchi method. Taguchi method is straightforward, easy to apply and has fast simulation run time. The dimension of the SNWFET device i.e. gate length (Lg ) , silicon nanowire radius (Rnw) and gate oxide thickness (Tax) are altered for a range of sizes and dimensions by using Taguchi approach to get the most optimum dimensions of the device. The electrical properties of the SNWFET device which are threshold voltage (Vth), on/off current ratio (Ion/Iott ratio), Subthreshold Swing (55), and Drain-Induced Barrier Lowering (DIBL) are extracted and analyzed based on the I-V characteristics. The general idea of the Taguchi technique is the set of electrical properties are statistically distributed into standard normal distribution and the mean and the standard deviation are determined. From the results obtained, with fixed thin Tax, as the Rnw is reduces and Lg is increases, the electrical performance of the SNWFET device is better in terms of its subthreshold swing, switching speed and DIBL. Better threshold is observed in nSNWFET device with smaller Rnw. The Ion/Iott ratio also shows better result with longer Lg . Lastly, from the statistical analytic of the device's electrical characteristics, the most optimum device dimensions of n-channel SNWFET device structure has been successfully identified which are Rnw at 3nm, Tax at 3nm, and Lg at 40nm with their electrical characteristics of Vt h , Ion/Iott ratio, 55 and DIBL are O.22V, I.06xI05 , 64.69mVIdee and = 80.27mV/V respectively.
format	Thesis
qualification_level	Master's degree
author	Wahab, Nurul Eryana
author_facet	Wahab, Nurul Eryana
author_sort	Wahab, Nurul Eryana
title	Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
title_short	Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
title_full	Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
title_fullStr	Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
title_full_unstemmed	Optimization of n-channel silicon nanowire field effect transistor using Taguchi method
title_sort	optimization of n-channel silicon nanowire field effect transistor using taguchi method
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2018
url	http://eprints.utm.my/id/eprint/78957/1/NurulEryanaWahabMFKE2018.pdf
_version_	1747818112966721536

Optimization of n-channel silicon nanowire field effect transistor using Taguchi method

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