Clustered two-dimensional mesh topology for large-scale network-on-chip architecture

Driven by the continuous scaling of Moore’s law, the number of processing cores in chip multiprocessors and systems-on-a-chip are expected to grow tremendously in the near future. Connecting the different components of a multiprocessor chip in a scalable and efficient way has become increasingly cha...

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Main Author:	Baboli, Mehdi
Format:	Thesis
Language:	English
Published:	2017
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/79138/1/MehdiBaboliPFKE2017.pdf
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id	my-utm-ep.79138
record_format	uketd_dc
spelling	my-utm-ep.791382018-09-30T08:23:13Z Clustered two-dimensional mesh topology for large-scale network-on-chip architecture 2017 Baboli, Mehdi TK Electrical engineering. Electronics Nuclear engineering Driven by the continuous scaling of Moore’s law, the number of processing cores in chip multiprocessors and systems-on-a-chip are expected to grow tremendously in the near future. Connecting the different components of a multiprocessor chip in a scalable and efficient way has become increasingly challenging. Current network-on-chip (NoC) topologies are adequate for small-size networks but are not optimized for large-scale networks. Transmitted packets inside a large NoC require longer route to reach their destinations, resulting in an increase in certain performance parameters such as latency and power consumption. Thus, it is necessary to develop a new topology appropriate for large-size NoCs. In this research, we proposed a cost-effective network topology for large-size NoCs that improves performance in terms of end-to-end latency. The topology, called RaMesh, consists of clusters of mesh networks. A routing algorithm suitable for this topology was also proposed. The RaMesh architecture together with mesh, torus, and clustered 2D-mesh were simulated using Noxim (NoC simulator), C for software NoC models, and Altera ModelSim for Verilog hardware models. Simulations were conducted under different network traffic and for a variety of network sizes. Experimental results showed that RaMesh performed better than equivalent 2D-mesh and torus topologies. RaMesh topology was also benchmarked against a clustered mesh topology. Average hop count in the proposed topology was at least 22.7% lower compared to the mesh and torus. Average latency was also decreased by at least 24.66% as compared to the mesh and torus. Finally, the saturation point for the proposed topology increased by at least 15% as compared to mesh and torus. 2017 Thesis http://eprints.utm.my/id/eprint/79138/ http://eprints.utm.my/id/eprint/79138/1/MehdiBaboliPFKE2017.pdf application/pdf en public phd doctoral Universiti Teknologi Malaysia, Faculty of Electrical Engineering Faculty of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Baboli, Mehdi Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
description	Driven by the continuous scaling of Moore’s law, the number of processing cores in chip multiprocessors and systems-on-a-chip are expected to grow tremendously in the near future. Connecting the different components of a multiprocessor chip in a scalable and efficient way has become increasingly challenging. Current network-on-chip (NoC) topologies are adequate for small-size networks but are not optimized for large-scale networks. Transmitted packets inside a large NoC require longer route to reach their destinations, resulting in an increase in certain performance parameters such as latency and power consumption. Thus, it is necessary to develop a new topology appropriate for large-size NoCs. In this research, we proposed a cost-effective network topology for large-size NoCs that improves performance in terms of end-to-end latency. The topology, called RaMesh, consists of clusters of mesh networks. A routing algorithm suitable for this topology was also proposed. The RaMesh architecture together with mesh, torus, and clustered 2D-mesh were simulated using Noxim (NoC simulator), C for software NoC models, and Altera ModelSim for Verilog hardware models. Simulations were conducted under different network traffic and for a variety of network sizes. Experimental results showed that RaMesh performed better than equivalent 2D-mesh and torus topologies. RaMesh topology was also benchmarked against a clustered mesh topology. Average hop count in the proposed topology was at least 22.7% lower compared to the mesh and torus. Average latency was also decreased by at least 24.66% as compared to the mesh and torus. Finally, the saturation point for the proposed topology increased by at least 15% as compared to mesh and torus.
format	Thesis
qualification_name	Doctor of Philosophy (PhD.)
qualification_level	Doctorate
author	Baboli, Mehdi
author_facet	Baboli, Mehdi
author_sort	Baboli, Mehdi
title	Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
title_short	Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
title_full	Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
title_fullStr	Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
title_full_unstemmed	Clustered two-dimensional mesh topology for large-scale network-on-chip architecture
title_sort	clustered two-dimensional mesh topology for large-scale network-on-chip architecture
granting_institution	Universiti Teknologi Malaysia, Faculty of Electrical Engineering
granting_department	Faculty of Electrical Engineering
publishDate	2017
url	http://eprints.utm.my/id/eprint/79138/1/MehdiBaboliPFKE2017.pdf
_version_	1747818155614404608

Clustered two-dimensional mesh topology for large-scale network-on-chip architecture

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