Design and analysis of a 2.5-GHz optical receiver analog front-end using geiger mode photodiode in a 0.13 μm CMOS process
The optical receiver analog front-end using geiger mode photodiode have several design challenges, especially in high-speed application. The parasitic capacitance (CPD) of the geiger mode photodiode (PD) is large, can be several pico farads which significantly limits the bandwidth (BW) of the geiger...
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| Format: | Thesis |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/79347/1/LeongChoonWeiMFKE2018.pdf |
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| Summary: | The optical receiver analog front-end using geiger mode photodiode have several design challenges, especially in high-speed application. The parasitic capacitance (CPD) of the geiger mode photodiode (PD) is large, can be several pico farads which significantly limits the bandwidth (BW) of the geiger mode photodiode. In addition, a very weak current signal which is generated by the geiger mode photodiode limits the number of photon count by the receiver circuit. To address this problem, the amplification stage followed the geiger mode photodiode must be designed to amplify the detected signal using a low voltage CMOS process device. Hence, low input impedance amplifier topologies such as common gate (CG) transimpedance amplifier (TIA) is usually employed. The applications of optical receiver are in high-speed optical communication system. Therefore, it is essential for the analog front-end (AFE) receiver (RX) which consists the PD and TIA to have a large bandwidth, usually in the range of several GHz. This project aims to design a 2.5 GHz optical AFE RX using PD in a 0.13 μm CMOS process. To comprehend the limitation of previous TIA topologies which have designed by the other researcher, these topologies are designed and simulated in lower supply voltage at 1.2 V and 0.13 μm CMOS process to assist the characterization of proposed TIA circuit for this project. Pre-layout simulation is performed and the circuit performance is analysed to define the topology that give the best performance to be used. Post layout simulation is performed on the chosen design. CG TIA is justified to be used in this project as the literature shows that it can achieve BW larger than 2.5 GHz compared to common source (CS) TIA. As a result, two TIAs which are the CG with common source active feedback (CSFB) and regulated cascode (RGC) are compared. With ideal resistor and ideal current source, the RGC outperformed CSFB in term of BW and gain. Hence, this project employed RGC topology to achieve the objective. The ideal circuit components are replaced with CMOS circuit to improve area and make the entire circuit fully on-chip. The BW achieved by the designed RGC TIA is 2.47 GHz with a TI gain of 53.8 dBΩ under large CPD of 2 pF. It is proven by this work that the RGC TIA is capable operating in the GHz frequency range with large CPD even the process shrink to 0.13 μm and the supply reduced to 1.2 V. |
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