High level dataflow network partitioning using stochastic algorithms
A dataflow actor network is a method of representing a design, showing clearly how data moves from one actor to another in graph form, suitable to represent designs such as a video streaming application. The design representation is written in the CAL Actor Language and the intent is to eventually i...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2018
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/79583/1/WooYitWengMFKE2018.pdf |
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| Summary: | A dataflow actor network is a method of representing a design, showing clearly how data moves from one actor to another in graph form, suitable to represent designs such as a video streaming application. The design representation is written in the CAL Actor Language and the intent is to eventually implement the design in hardware, more specifically, Field Programmable Gate Arrays (FPGA). Instead of using a large FPGA to fit the entire design, the design is seperated into smaller blocks to be implemented in multiple smaller FPGAs. This has multiple advantages such as savings in cost and time as well as allowing more flexibility according to the design need and available resources. The caveat of this design approach is that the connections between FPGAs would incur some latency and noise. As such, the actors in the design need to be partitioned accordingly to minimize these inter-FPGA connections. This project will be investigating two partitioning algorithms, namely the Particle Swarm Optimization (PSO) and Ant Colony Optimization (ACO) algorithms, to see which of these stochastic algorithms is better at partitioning the target design. Traditionally, partitioning is done using the cut cost as the optimized metric. While this would lead to less physical wires going across FPGAs, this could result in critical connections being compromised as it needs to traverse FPGAs. As such, this project will also investigate the feasibility of using communication rate as the partitioning criterion to better ensure that the connections between FPGAs are not critical such that the penalty can be tolerated. This project will use the profiles of a basic FIR Digital Filter as well as larger HEVC Decoder and MPEG-4 AVC Decoder test cases. The partitioning algorithms will be written in Java, using information regarding the actors and connections that are in the profile of each design. The results are analyzed to determine which algorithm is more suited to separate the design into balanced partitions as well as whether communication rate is a better partitioning criterion than cut cost for certain applications. The results obtained will also be compared with results obtained using the deteministic Fiduccia-Mattheyses (FM) algorithm. |
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