Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method

The scaling of conventional transistor according to Moore’s Law is predicted to reach its limitation in the future. The conventional transistor using silicon material particularly at nanoscale channel has experienced the short channel effect (SCE), which leads to increase in the leakage current. The...

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Main Author:	Loy, Ying Ting
Format:	Thesis
Language:	English
Published:	2020
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/93027/1/LoyYingTingMSKE2020.pdf
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id	my-utm-ep.93027
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spelling	my-utm-ep.930272021-11-07T06:00:34Z Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method 2020 Loy, Ying Ting TK Electrical engineering. Electronics Nuclear engineering The scaling of conventional transistor according to Moore’s Law is predicted to reach its limitation in the future. The conventional transistor using silicon material particularly at nanoscale channel has experienced the short channel effect (SCE), which leads to increase in the leakage current. Therefore, alternative device structure and advanced material are needed to overcome the SCE and reduce the leakage current (Il e a k ) with regards to the transistor performance. In this project, a method to control the leakage current in ultranarrow 10 nm FinFET using High-K dielectric material is proposed. The device’s fabrication and electrical characterization are then executed using TCAD Sentaurus from Synopsys. Optimization of the process parameters using L9 Taguchi method and finally prediction of the best combination of process parameters in order to obtain the minimum leakage current ( I l e a k ) in the 10 nm FinFET. There are four process parameters were varied, which are the fins dimension (fin height and width), channel concentration and oxide thickness. Smaller-the-Better (STB) Signal - to -noise ratio (SNR) and the Analysis of Variance (ANOVA) is used to study the performance characteristic and finally obtain the best combination of process parameters in order for the device to perform at its best performance, that will later benchmarked with predicted data from International Technology Roadmap for Semiconductors (ITRS) and previous published results. The optimization is expected to result in the attainment of the lower leakage current value in order to increase the speed performance of the device. 2020 Thesis http://eprints.utm.my/id/eprint/93027/ http://eprints.utm.my/id/eprint/93027/1/LoyYingTingMSKE2020.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135936 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Loy, Ying Ting Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
description	The scaling of conventional transistor according to Moore’s Law is predicted to reach its limitation in the future. The conventional transistor using silicon material particularly at nanoscale channel has experienced the short channel effect (SCE), which leads to increase in the leakage current. Therefore, alternative device structure and advanced material are needed to overcome the SCE and reduce the leakage current (Il e a k ) with regards to the transistor performance. In this project, a method to control the leakage current in ultranarrow 10 nm FinFET using High-K dielectric material is proposed. The device’s fabrication and electrical characterization are then executed using TCAD Sentaurus from Synopsys. Optimization of the process parameters using L9 Taguchi method and finally prediction of the best combination of process parameters in order to obtain the minimum leakage current ( I l e a k ) in the 10 nm FinFET. There are four process parameters were varied, which are the fins dimension (fin height and width), channel concentration and oxide thickness. Smaller-the-Better (STB) Signal - to -noise ratio (SNR) and the Analysis of Variance (ANOVA) is used to study the performance characteristic and finally obtain the best combination of process parameters in order for the device to perform at its best performance, that will later benchmarked with predicted data from International Technology Roadmap for Semiconductors (ITRS) and previous published results. The optimization is expected to result in the attainment of the lower leakage current value in order to increase the speed performance of the device.
format	Thesis
qualification_level	Master's degree
author	Loy, Ying Ting
author_facet	Loy, Ying Ting
author_sort	Loy, Ying Ting
title	Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
title_short	Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
title_full	Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
title_fullStr	Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
title_full_unstemmed	Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
title_sort	optimization of progress parameters for lower leakage current in 10 nm finfet using taguchi method
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2020
url	http://eprints.utm.my/id/eprint/93027/1/LoyYingTingMSKE2020.pdf
_version_	1747818629950341120

Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method

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